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公开(公告)号：US07180331B2
公开(公告)日：2007-02-20
申请号：US11028934
申请日：2005-01-03
申请人： Vincent Gosmain , David Bernard
发明人： Vincent Gosmain , David Bernard
IPC分类号： H03K19/0175
CPC分类号： H03K19/00315 , H01L2924/0002 , H01L2924/00
摘要： An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the gate of the PMOS pull-up transistor to an input/output node in response to an input signal having a voltage greater than approximately the first supply voltage. A well bias control circuit is coupled to the PMOS pull-up transistor and to a well drive transistor to couple the nwell terminal to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage.
摘要翻译： 具有输入模式并且耦合在第一和第二电源电压之间的输入/输出（I / O）缓冲器包括以n阱制造的PMOS上拉晶体管和耦合到PMOS上拉栅极的栅极偏置控制晶体管 晶体管，用于响应于具有大于大约第一电源电压的电压的输入信号，将PMOS上拉晶体管的栅极耦合到输入/输出节点。 阱偏置控制电路耦合到PMOS上拉晶体管和阱驱动晶体管，以响应于具有大致等于或小于第一电源电压的电压的输入信号将n阱端子耦合到第一电源电压。
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公开(公告)号：US20060066355A1
公开(公告)日：2006-03-30
申请号：US11028934
申请日：2005-01-03
申请人： Vincent Gosmain , David Bernard
发明人： Vincent Gosmain , David Bernard
IPC分类号： H03K19/094
CPC分类号： H03K19/00315 , H01L2924/0002 , H01L2924/00
摘要： An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the gate of the PMOS pull-up transistor to an input/output node in response to an input signal having a voltage greater than approximately the first supply voltage. A well bias control circuit is coupled to the PMOS pull-up transistor and to a well drive transistor to couple the nwell terminal to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage.
摘要翻译： 具有输入模式并且耦合在第一和第二电源电压之间的输入/输出（I / O）缓冲器包括以n阱制造的PMOS上拉晶体管，以及耦合到PMOS上拉栅极的栅极偏置控制晶体管 晶体管，用于响应于具有大于大约第一电源电压的电压的输入信号，将PMOS上拉晶体管的栅极耦合到输入/输出节点。 阱偏置控制电路耦合到PMOS上拉晶体管和阱驱动晶体管，以响应于具有大致等于或小于第一电源电压的电压的输入信号将n阱端子耦合到第一电源电压。
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公开(公告)号：US20070127283A1
公开(公告)日：2007-06-07
申请号：US11375839
申请日：2006-03-14
申请人： Vincent Gosmain , Florent Garcia
发明人： Vincent Gosmain , Florent Garcia
IPC分类号： G11C17/00
摘要： An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.
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公开(公告)号：US07606058B2
公开(公告)日：2009-10-20
申请号：US11923434
申请日：2007-10-24
申请人： Vincent Gosmain , Florent Garcia
发明人： Vincent Gosmain , Florent Garcia
IPC分类号： G11C17/00
摘要： An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.
摘要翻译： 提供针对入侵者的保护的独立反熔丝电池包括反熔丝，感测电路，反馈电路，程序电路和阻塞电路。 阻塞电路阻止任何编程电压输入信号到反熔丝装置的访问，如果反熔丝被预先熔断并且当电力施加到电池时。 在示例性实施例中，反熔断器单元仅使用单个外部访问引脚。 一旦反熔丝装置被熔断并且在随后的上电操作期间，就防止了入侵。
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公开(公告)号：US20080043511A1
公开(公告)日：2008-02-21
申请号：US11923434
申请日：2007-10-24
申请人： Vincent Gosmain , Florent Garcia
发明人： Vincent Gosmain , Florent Garcia
IPC分类号： G11C17/00
摘要： An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.
摘要翻译： 提供针对入侵者的保护的独立反熔丝电池包括反熔丝，感测电路，反馈电路，程序电路和阻塞电路。 阻塞电路阻止任何编程电压输入信号到反熔丝装置的访问，如果反熔丝被预先熔断并且当电力施加到电池时。 在示例性实施例中，反熔断器单元仅使用单个外部访问引脚。 一旦反熔丝装置被熔断并且在随后的上电操作期间，就防止了入侵。
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公开(公告)号：US07236043B2
公开(公告)日：2007-06-26
申请号：US11252180
申请日：2005-10-17
申请人： Mathew T. Wich , Vincent Gosmain
发明人： Mathew T. Wich , Vincent Gosmain
IPC分类号： H01H85/00
CPC分类号： G11C17/18
摘要： An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the VDD node of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the VDD node of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage and tampering. The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low.
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公开(公告)号：US07304878B2
公开(公告)日：2007-12-04
申请号：US11375839
申请日：2006-03-14
申请人： Vincent Gosmain , Florent Garcia
发明人： Vincent Gosmain , Florent Garcia
IPC分类号： G11C17/00
摘要： An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.
摘要翻译： 提供针对入侵者的保护的独立反熔丝电池包括反熔丝，感测电路，反馈电路，程序电路和阻塞电路。 阻塞电路阻止任何编程电压输入信号到反熔丝装置的访问，如果反熔丝被预先熔断并且当电力施加到电池时。 在示例性实施例中，反熔断器单元仅使用单个外部访问引脚。 一旦反熔丝装置被熔断并且在随后的上电操作期间，就防止了入侵。
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公开(公告)号：US20070085593A1
公开(公告)日：2007-04-19
申请号：US11252180
申请日：2005-10-17
申请人： Mathew Wich , Vincent Gosmain
发明人： Mathew Wich , Vincent Gosmain
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the VDD node of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the VDD node of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage and tampering. The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low.
摘要翻译： 反熔丝编程，保护和感测装置包括用于编程和保护反熔丝的控制电路。 最初构造为低电导率路径的反熔丝可通过在反熔丝的端子上施加升高的电压而被编程为高电导率路径。 对反熔丝编程，保护和感测装置的导通控制部分的V DD端节点施加0伏电压允许将用于编程的高电压施加到反熔丝。 在向导通控制电路的V DD端子施加标称工作电压时，防熔接和相邻的读出放大器电路被保护以防过电压和篡改。 感测放大器向反熔丝提供感测电流，测量反熔丝输入端的电压，并且如果测量的电压电平低，则确定编程状态。
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