公开(公告)号：US08248130B2

公开(公告)日：2012-08-21

申请号：US12786496

申请日：2010-05-25

申请人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinish Chandra Tripathi ,  Sanjay Kumar Wadhwa

发明人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinish Chandra Tripathi ,  Sanjay Kumar Wadhwa

IPC分类号： H03K3/17 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

摘要翻译： 用于校正由时钟发生器产生的时钟信号的占空比的占空比校正电路包括互补缓冲链，电平移位器电路和自偏置电路。 具有失真占空比的时钟信号及其补码提供给电平移位器电路。 电平移位器电路减小时钟信号和补码的电压幅值，并产生电平移位信号。 电平移位信号被提供给差分放大器，该差分放大器产生指示占空比中的失真幅度的控制信号。 控制信号用于校正时钟信号的占空比。 自偏置电路用于偏置差分放大器。