摘要:
The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要:
An electronically implemented method includes multiplying a number A, and a number B, where A is composed of segments ai and B is composed of segments bj where i and j are integers greater than 1. The multiplying includes determining partial product values for at least some of aibj and determining a sum of partial product values for aibj and ajbi where ai=bj and bj=ai for respective values of i and j, by multiplying one of (1) aibj and (2) ajbi by two. A sum is determined and stored in a memory storage element of the determined partial product values and the determined sum of partial product values for aibj and ajbi.
摘要:
The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要:
The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要:
The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要:
The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要:
The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要:
The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要:
In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要:
A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.