公开(公告)号：US08181258B2

公开(公告)日：2012-05-15

申请号：US10723150

申请日：2003-11-26

申请人： Vinoj N. Kumar ,  Narender R. Vangati

发明人： Vinoj N. Kumar ,  Narender R. Vangati

IPC分类号： G06F21/00

CPC分类号： H04L63/0227 ,  H04L63/0245

摘要： Techniques are disclosed for generating a representation of an access control list, the representation being utilizable in a network processor or other type of processor to perform packet filtering or other type of access control list based function. A plurality of rules of the access control list are determined, each of at least a subset of the rules having a plurality of fields and a corresponding action, and the rules are processed to generate a multi-level tree representation of the access control list, in which each of one or more of the levels of the tree representation is associated with a corresponding one of the fields. At least one level of the tree representation other than a root level of the tree representation comprises a plurality of nodes, with at least two of the nodes at that level each having a separate matching table associated therewith.

摘要翻译： 公开了用于生成访问控制列表的表示的技术，所述表示可在网络处理器或其他类型的处理器中使用以执行分组过滤或基于其他类型的基于访问控制列表的功能。 确定访问控制列表的多个规则，规则的至少一个子集中的每一个具有多个字段和对应的动作，并且处理规则以生成访问控制列表的多级树表示， 其中树形表示的一个或多个级别中的每一个与相应的一个字段相关联。 除了树表示的根级别之外的树形表示的至少一个级别包括多个节点，其中该级别的至少两个节点具有与之相关联的单独的匹配表。

公开(公告)号：US08031706B2

公开(公告)日：2011-10-04

申请号：US11263300

申请日：2005-10-31

申请人： Vinoj N. Kumar ,  Robert J. Munoz

发明人： Vinoj N. Kumar ,  Robert J. Munoz

IPC分类号： H04L12/56

CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L45/7453 ,  H04L49/3009 ,  H04L49/602

摘要： A network processor for determining one or more network operations to be performed on a packet of data in a network comprises processing circuitry and protocol indicator circuitry. The packet of data contains information populating a plurality of protocol header fields. Moreover, the protocol indicator circuitry comprises a plurality of memory elements, each memory element associated with a protocol header field in the plurality of protocol header fields. The processing circuitry determines the one or more network operations to be performed on the packet of data at least in part by addressing one or more lookup tables with the contents of a subset of the plurality of protocol header fields in the packet. This subset is determined by reference to the memory elements in the protocol indicator circuitry. Each memory element is capable of being programmed to indicate whether the associated protocol header field is to be utilized by the processing circuitry in addressing the one or more lookup tables.

摘要翻译： 用于确定要对网络中的数据分组执行的一个或多个网络操作的网络处理器包括处理电路和协议指示符电路。 数据包包含填充多个协议报头字段的信息。 此外，协议指示符电路包括多个存储器元件，每个存储器元件与多个协议报头字段中的协议报头字段相关联。 处理电路至少部分地通过利用分组中的多个协议报头字段的子集的内容寻址一个或多个查找表来确定要对数据包执行的一个或多个网络操作。 该子集通过参考协议指示符电路中的存储元件来确定。 每个存储器元件能够被编程以指示处理电路在寻址一个或多个查找表中是否使用关联的协议报头字段。

公开(公告)号：US08433784B2

公开(公告)日：2013-04-30

申请号：US10620258

申请日：2003-07-15

申请人： Vinoj N. Kumar ,  Kaushik Nath

发明人： Vinoj N. Kumar ,  Kaushik Nath

IPC分类号： G06F15/16 ,  G06F17/50

CPC分类号： H04L43/50

摘要： A traffic generator is disclosed which generates a first type of traffic in accordance with a given distribution, and generates a second type of traffic that includes at least one traffic burst. The traffic burst is generated based at least in part on an amount of the first type of traffic generated over one or more time intervals. For example, in an illustrative embodiment, generation of the second type of traffic involves accumulating traffic over one or more of the time intervals for which the first type of traffic is generated, and generating the traffic burst based at least in part on the accumulated traffic.

摘要翻译： 公开了根据给定分布生成第一类型的业务的业务生成器，并且生成包括至少一个业务突发的第二类型业务。 至少部分地基于在一个或多个时间间隔上生成的第一类型的流量的量来生成流量突发。 例如，在说明性实施例中，第二类型的业务的产生涉及在产生第一类型的业务的时间间隔中的一个或多个时间段累积业务，并且至少部分地基于累积流量来生成业务突发 。

公开(公告)号：US08254267B2

公开(公告)日：2012-08-28

申请号：US10620044

申请日：2003-07-15

申请人： D Srivatsan ,  Vinoj N. Kumar ,  Kaushik Nath ,  Srinivasan Rangarajan ,  Chandramouleeswaran Sankaran

发明人： D Srivatsan ,  Vinoj N. Kumar ,  Kaushik Nath ,  Srinivasan Rangarajan ,  Chandramouleeswaran Sankaran

IPC分类号： H04L12/26

CPC分类号： H04L43/50

摘要： A traffic generator generates a plurality of traffic flows, with each of the traffic flows being associatable with one or more of a plurality of output interfaces of the traffic generator. In an illustrative embodiment, each of the output interfaces may have any desired combination of the traffic flows associated therewith. The traffic flows may be generated based on user selection of at least one of a protocol encapsulation, a packet size distribution model, a packet arrival time distribution model, a traffic model, and a packet payload description. Information characterizing one or more of the traffic flows may be stored as a traffic file in a memory associated with the traffic generator.

摘要翻译： 业务发生器产生多个业务流，其中每个业务流可与业务发生器的多个输出接口中的一个或多个相关联。 在说明性实施例中，每个输出接口可以具有与其相关联的业务流的任何期望的组合。 可以基于用户选择协议封装，分组大小分布模型，分组到达时间分布模型，业务模型和分组有效载荷描述中的至少一个来生成业务流。 表征一个或多个业务流的信息可以作为业务文件存储在与业务发生器相关联的存储器中。

公开(公告)号：US07873506B2

公开(公告)日：2011-01-18

申请号：US10609781

申请日：2003-06-30

申请人： Paul N. Hintikka ,  Sileshi Kassa ,  Vinoj N. Kumar ,  Ravi K. Mandava

发明人： Paul N. Hintikka ,  Sileshi Kassa ,  Vinoj N. Kumar ,  Ravi K. Mandava

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022

摘要： The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.

摘要翻译： 使用基于软件的开发工具来模拟包括多个集成电路或其他电路元件的电子系统的操作，所述开发工具提供用于同时模拟具有潜在不同的时钟速度，延迟或其他特性的多个电路元件的通用框架。 在基于软件的开发工具中提供的一个或多个接口允许与一个或多个电路元件相关联的处理事件的注册。 基于软件的开发工具进一步操作以确定用于给定模拟的系统时钟，并且以考虑到系统时钟与一个或多个电路元件时钟之间的差异的方式调度相关联的处理事件的执行，以便 以保持处理事件相对于确定的系统时钟的执行的一致性。

公开(公告)号：US07822589B2

公开(公告)日：2010-10-26

申请号：US10620045

申请日：2003-07-15

申请人： Rajarshi Bhattacharya ,  Sriram Gorti ,  Vinoj N. Kumar ,  Chandramouleeswaran Sankaran ,  Tirthendu Sarkar

发明人： Rajarshi Bhattacharya ,  Sriram Gorti ,  Vinoj N. Kumar ,  Chandramouleeswaran Sankaran ,  Tirthendu Sarkar

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A software-based development tool is operative to automatically determine an appropriate simulation configuration for a multistage switch fabric or other multiple circuit element electronic system. The development tool includes an interface permitting user control of one or more configurable parameters of the electronic system, and automatically generates a simulation configuration for the electronic system based on current values of the configurable parameters. The simulation configuration is advantageously generated without requiring further user input, and specifies interconnections between the circuit elements which satisfy the current values of the configurable parameters.

摘要翻译： 基于软件的开发工具可操作以自动确定多级交换结构或其他多电路元件电子系统的适当模拟配置。 开发工具包括允许用户控制电子系统的一个或多个可配置参数的界面，并且基于可配置参数的当前值自动生成电子系统的模拟配置。 有利地生成模拟配置，而不需要进一步的用户输入，并且指定满足可配置参数的当前值的电路元件之间的互连。