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1.发明授权Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source 失效使用部分存储地址数据索引的条目对数据消息进行存储访问验证，其中包含消息源的允许的地址范围验证
公开(公告)号：US5964835A
公开(公告)日：1999-10-12
申请号：US482618
申请日：1995-06-07
申请人： Daniel L. Fowler , William Edward Baker , William Patterson Bunton , Gary F. Campbell , Richard W. Cutts, Jr. , David J. Garcia , Paul N. Hintikka , Robert W. Horst , Geoffrey I. Iswandhi , David P. Sonnier , William Joel Watson , Frank A. Williams
发明人： Daniel L. Fowler , William Edward Baker , William Patterson Bunton , Gary F. Campbell , Richard W. Cutts, Jr. , David J. Garcia , Paul N. Hintikka , Robert W. Horst , Geoffrey I. Iswandhi , David P. Sonnier , William Joel Watson , Frank A. Williams
IPC分类号： G06F11/18 , G01R31/317 , G01R31/3185 , G06F1/12 , G06F9/52 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/273 , G06F12/08 , G06F12/14 , G06F12/16 , G06F13/00 , H04L12/56 , H04L29/14
CPC分类号： G01R31/31727 , G06F1/12 , G06F11/10 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1687 , G06F12/0815 , G06F12/1483 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40 , G01R31/318533 , G06F11/004 , G06F11/1044 , G06F11/167 , G06F11/1683 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F2201/845 , H04L12/56
摘要： A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.
摘要翻译： 多处理器系统包括多个中央处理单元（CPU）和至少一个输入/输出（I / O）设备，其通过路由设备互连，用于在其间传送分组消息。 消息包含标识消息的源和目的地的地址信息，并且还可以包含写入或读取CPU的存储的请求。 通过使用由每个CPU维护的多个条目中包含的访问验证信息的访问验证方法来提供对错误读取或写入的保护。 每个条目通过确定系统的哪些元素已读取和/或将wccss写入该CPU的内存来进行验证，而不会拒绝该内存访问。
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公开(公告)号：US5751932A
公开(公告)日：1998-05-12
申请号：US485217
申请日：1995-06-07
申请人： Robert W. Horst , William Edward Baker , Randall G. Banton , John Michael Brown , William F. Bruckert , William Patterson Bunton , Gary F. Campbell , John Deane Coddington , Richard W. Cutts, Jr. , Barry Lee Drexler , Harry Frank Elrod , Daniel L. Fowler , David J. Garcia , Paul N. Hintikka , Geoffrey I. Iswandhi , Douglas Eugene Jewett , Curtis Willard Jones, Jr. , James Stevens Klecka , John C. Krause , Stephen G. Low , Susan Stone Meredith , Steven C. Meyers , David P. Sonnier , William Joel Watson , Patricia L. Whiteside , Frank A. Williams , Linda Ellen Zalzala
发明人： Robert W. Horst , William Edward Baker , Randall G. Banton , John Michael Brown , William F. Bruckert , William Patterson Bunton , Gary F. Campbell , John Deane Coddington , Richard W. Cutts, Jr. , Barry Lee Drexler , Harry Frank Elrod , Daniel L. Fowler , David J. Garcia , Paul N. Hintikka , Geoffrey I. Iswandhi , Douglas Eugene Jewett , Curtis Willard Jones, Jr. , James Stevens Klecka , John C. Krause , Stephen G. Low , Susan Stone Meredith , Steven C. Meyers , David P. Sonnier , William Joel Watson , Patricia L. Whiteside , Frank A. Williams , Linda Ellen Zalzala
IPC分类号： G06F11/18 , G01R31/317 , G01R31/3185 , G06F1/12 , G06F9/52 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/273 , G06F12/08 , G06F12/14 , G06F12/16 , G06F13/00 , H04L12/56 , H04L29/14
CPC分类号： G01R31/31727 , G06F1/12 , G06F11/10 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1687 , G06F12/0815 , G06F12/1483 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40 , G01R31/318533 , G06F11/004 , G06F11/1044 , G06F11/167 , G06F11/1683 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F2201/845 , H04L12/56
摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 CPU被构造为以两种模式之一操作：两个CPU彼此独立地操作的单工模式，以及CPU以锁步同步操作的双工模式，以基本上执行相同指令流的每条指令 同一时间。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。
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3.发明授权
公开(公告)号：US6151684A
公开(公告)日：2000-11-21
申请号：US48938
申请日：1998-03-26
CPC分类号： G06F11/2028 , G06F11/2017 , G06F11/2033 , G06F11/1658 , G06F11/203
摘要： A system area network computer system architecture is structured as a single system image cluster operating system to offer an opportunity to increase the availability to I/O devices in the system. The computing system comprises a number of processor units coupled to a plurality of input/output (I/O) elements by a routing fabric that provides each of the processor elements with access to any one of the I/O elements. Using a Transparent Network Computing extension to a highly available version of UNIX System V Release 4.2, the system provides a higher degree of availability to I/O devices by providing for the takeover of their controlling entity.
摘要翻译： 系统区域网络计算机系统架构被构造为单个系统映像集群操作系统，以提供增加系统中I / O设备的可用性的机会。 计算系统包括多个处理器单元，其通过路由结构耦合到多个输入/输出（I / O）元件，该布线结构为每个处理器元件提供对任何一个I / O元件的访问。 使用透明网络计算扩展到UNIX System V Release 4.2的高可用性版本，该系统通过提供其控制实体的接管为I / O设备提供更高程度的可用性。
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4.发明授权Interrupt message delivery identified by storage location of received interrupt data 失效中断消息传递由接收到的中断数据的存储位置标识
公开(公告)号：US5675807A
公开(公告)日：1997-10-07
申请号：US481749
申请日：1995-06-07
申请人： Geoffrey I. Iswandhi , William Edward Baker , William Patterson Bunton , John Deane Coddington , Daniel L. Fowler , David J. Garcia , Paul N. Hintikka , Susan Stone Meredith , Stephen H. Miller , David Paul Sonnier , William Joel Watson , Frank A. Williams
发明人： Geoffrey I. Iswandhi , William Edward Baker , William Patterson Bunton , John Deane Coddington , Daniel L. Fowler , David J. Garcia , Paul N. Hintikka , Susan Stone Meredith , Stephen H. Miller , David Paul Sonnier , William Joel Watson , Frank A. Williams
IPC分类号： G06F11/18 , G01R31/317 , G01R31/3185 , G06F1/12 , G06F9/52 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/273 , G06F12/08 , G06F12/14 , G06F12/16 , G06F13/00 , H04L12/56 , H04L29/14
CPC分类号： G01R31/31727 , G06F1/12 , G06F11/10 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1687 , G06F12/0815 , G06F12/1483 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40 , G01R31/318533 , G06F11/004 , G06F11/1044 , G06F11/167 , G06F11/1683 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F2201/845 , H04L12/56
摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.
摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或与系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息分组，并存储在存储器中的中断队列中。 中断数据的存储将启动内部中断以通知接收CPU。 然后，接收CPU可以访问中断队列，检查中断数据，并确定要采取的操作。
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5.发明授权Simulation framework with support for multiple integrated circuits having potentially differing characteristics 有权具有支持具有潜在不同特性的多个集成电路的仿真框架公开(公告)号：US07873506B2
公开(公告)日：2011-01-18
申请号：US10609781
申请日：2003-06-30
CPC分类号： G06F17/5022
摘要： The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.
摘要翻译： 使用基于软件的开发工具来模拟包括多个集成电路或其他电路元件的电子系统的操作，所述开发工具提供用于同时模拟具有潜在不同的时钟速度，延迟或其他特性的多个电路元件的通用框架。 在基于软件的开发工具中提供的一个或多个接口允许与一个或多个电路元件相关联的处理事件的注册。 基于软件的开发工具进一步操作以确定用于给定模拟的系统时钟，并且以考虑到系统时钟与一个或多个电路元件时钟之间的差异的方式调度相关联的处理事件的执行，以便 以保持处理事件相对于确定的系统时钟的执行的一致性。
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