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    Method for performing a parallel static timing analysis using thread-specific sub-graphs
    1.
    发明授权
    Method for performing a parallel static timing analysis using thread-specific sub-graphs 有权
    使用线程特定子图执行并行静态时序分析的方法

    公开(公告)号：US08381150B2

    公开(公告)日：2013-02-19

    申请号：US13151295

    申请日：2011-06-02

    申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

    摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

    摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

    Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs
    2.
    发明申请
    Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs 有权
    使用线程特定子图执行并行静态时序分析的方法

    公开(公告)号：US20120311515A1

    公开(公告)日：2012-12-06

    申请号：US13151295

    申请日：2011-06-02

    申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

    摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

    摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

    System and method for correlated process pessimism removal for static timing analysis
    5.
    发明授权
    System and method for correlated process pessimism removal for static timing analysis 失效
    静态时序分析相关过程悲观消除的系统和方法

    公开(公告)号：US07117466B2

    公开(公告)日：2006-10-03

    申请号：US10665273

    申请日：2003-09-18

    申请人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.

    摘要翻译： 描述了静态时序分析中消除悲观情绪的方法。 延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。 根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。 分析以路径为基础进行。 通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。 此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。 另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS
    6.
    发明申请
    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS 失效
    基于路径的混合多角度静态时序分析评估统计灵敏度信息的方法和系统

    公开(公告)号：US20080209373A1

    公开(公告)日：2008-08-28

    申请号：US11679251

    申请日：2007-02-27

    申请人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    发明人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

    摘要翻译： 公开了用于分析集成电路的定时设计的方法，系统和计算机程序产品。 根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择通过静态定时测试的静态定时测试点的定时路径; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。

    System and method for correlated process pessimism removal for static timing analysis
    7.
    发明申请
    System and method for correlated process pessimism removal for static timing analysis 失效
    静态时序分析相关过程悲观消除的系统和方法

    公开(公告)号：US20050066297A1

    公开(公告)日：2005-03-24

    申请号：US10665273

    申请日：2003-09-18

    申请人： Kerim Kalafala ,  Peihua Qi ,  David Hathaway ,  Alexander Suess ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Peihua Qi ,  David Hathaway ,  Alexander Suess ,  Chandramouli Visweswariah

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.

    摘要翻译： 描述了静态时序分析中消除悲观情绪的方法。 延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。 根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。 分析以路径为基础进行。 通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。 此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。 另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。