利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

64 条记录 (耗时 0.03 秒)

    Method for performing a parallel static timing analysis using thread-specific sub-graphs
    1.
    发明授权
    Method for performing a parallel static timing analysis using thread-specific sub-graphs 有权
    使用线程特定子图执行并行静态时序分析的方法

    公开(公告)号：US08381150B2

    公开(公告)日：2013-02-19

    申请号：US13151295

    申请日：2011-06-02

    申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

    摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

    摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

    Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs
    2.
    发明申请
    Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs 有权
    使用线程特定子图执行并行静态时序分析的方法

    公开(公告)号：US20120311515A1

    公开(公告)日：2012-12-06

    申请号：US13151295

    申请日：2011-06-02

    申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

    摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

    摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

    Method of measuring the impact of clock skew on slack during a statistical static timing analysis
    5.
    发明授权
    Method of measuring the impact of clock skew on slack during a statistical static timing analysis 有权
    在统计静态时序分析期间测量时钟偏移对松弛影响的方法

    公开(公告)号：US08578310B2

    公开(公告)日：2013-11-05

    申请号：US12857591

    申请日：2010-08-17

    申请人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

    摘要翻译： 计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。 时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数 到锁定延迟，测试保护时间和测试调整。 该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行​​偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。

    Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis
    6.
    发明申请
    Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis 有权
    在统计静态时序分析中测量时钟偏移对松弛影响的方法

    公开(公告)号：US20120047477A1

    公开(公告)日：2012-02-23

    申请号：US12857591

    申请日：2010-08-17

    申请人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

    摘要翻译： 计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。 时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数 到锁定延迟，测试保护时间和测试调整。 该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行​​偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。

    Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits
    8.
    发明授权
    Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits 有权
    在数字电路的统计静态时序分析中表征和传播变分电压波形

    公开(公告)号：US07814448B2

    公开(公告)日：2010-10-12

    申请号：US11733058

    申请日：2007-04-09

    申请人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.

    摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

    REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS
    9.
    发明申请
    REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS 有权
    在数字电路的统计静态时序分析中代表和传播变量电压波形

    公开(公告)号：US20080250370A1

    公开(公告)日：2008-10-09

    申请号：US11733058

    申请日：2007-04-09

    申请人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.

    摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

    Yield computation and optimization for selective voltage binning
    10.
    发明授权
    Yield computation and optimization for selective voltage binning 有权
    选择性电压合并的产量计算和优化

    公开(公告)号：US08781792B2

    公开(公告)日：2014-07-15

    申请号：US12610291

    申请日：2009-10-31

    申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F11/30

    CPC分类号： G06F17/5045 ,  G06F2217/10 ,  G06F2217/82

    摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.

    摘要翻译： 提供了用于提高制造芯片的参数芯片产量的技术。 在一方面，提供了一种用于优化参数芯片产量的方法。 该方法包括以下步骤。 基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。 然后确定计算的参数芯片产量是否是最佳的。 如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。 否则，binning方案保持不变。