公开(公告)号：US3950654A

公开(公告)日：1976-04-13

申请号：US523809

申请日：1974-11-14

申请人： Walter F. Broedner ,  Ravinder K. Bhatnagar ,  W. Eugene Hill ,  Daniel W. Tjoa

发明人： Walter F. Broedner ,  Ravinder K. Bhatnagar ,  W. Eugene Hill ,  Daniel W. Tjoa

IPC分类号： G06F1/24 ,  H03K3/356 ,  H03K17/22 ,  H03K19/017 ,  H03K19/0944 ,  H03K1/12 ,  H03K5/153

CPC分类号： H03K17/223 ,  G06F1/24 ,  H03K19/01721 ,  H03K19/09443 ,  H03K3/356008 ,  Y10T307/735

摘要： An initializing circuit for automatically providing a pulse of a duration sufficient to initialize all the relevant storage elements in an electronic calculator computing system having one or two power supplies. It comprises a power-on pulse generator controlled by two phase clock buffers utilizing a feed-back loop including a bit of delay to guarantee a minimum of one bit time duration for the power-on level. The two phase clock buffers are activated at turn-on to remain in a steady state by a power-on level detecting sub-circuit to control the pulse generator. When a one bit pulse is insufficient to initialize the system, a flip-flop and a counter may be used to generate a longer pulse.