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公开(公告)号：US5995425A
公开(公告)日：1999-11-30
申请号：US898826
申请日：1997-07-23
IPC分类号： G01R31/3185 , G11C7/00
CPC分类号： G01R31/318536 , Y10S257/903
摘要： A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. Using the elimination process for elements which are difficult to be extracted in Boolean form the logic around and inside a memory structure can be verified. The resultant register array hardware organization can be verified to all pins and nets up to the storage element.
摘要翻译： 硬件设计技术允许检查具有嵌入式阵列和寄存器的大型宏的元素和原理图的设计系统语言（DSL）规范。 硬件组织将逻辑验证的CPU时间缩小到指数级数量级，而不会引发验证过程或逻辑仿真。 硬件组织由水平字层而不是位级组成。 使用布尔形式难以提取的元素的消除过程可以验证存储器结构周围和内部的逻辑。 结果寄存器阵列硬件组织可以验证所有引脚和网络直到存储元件。
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2.发明授权
公开(公告)号：US6151266A
公开(公告)日：2000-11-21
申请号：US943738
申请日：1997-10-03
CPC分类号： G06F9/30141 , G06F9/3869 , G11C8/16
摘要： Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal generation, true and complement address buffer, decoder and wordline drivers, and write enable circuits employ the advantages of a fully custom designed methodology with self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques. Individual write enable pulses applied to respective input ports of a multiport register cell are effective to establish a priority among those input ports. In this design, the priority of the B-write-port over the A-write-port is established when both write ports address the same register. The present invention provides an effective input isolation/decoupling circuit technique which allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in effective input isolation scheme.
摘要翻译： 公开了用于高性能异步多端口寄存器文件的自复位和写控制电路。 高速写入操作通过静态数据输入和动态数据控制电路的组合来实现。 写时序信号产生，真实和补码地址缓冲器，解码器和字线驱动器以及写使能电路采用具有自复位互补金属氧化物半导体（SRCMOS）电路技术的完全定制设计的方法的优点。 施加到多端口寄存器单元的相应输入端口的单独写使能脉冲对于在这些输入端口之间建立优先级是有效的。 在这种设计中，当写入端口寻址同一个寄存器时，建立B写入端口对A写入端口的优先级。 本发明提供一种有效的输入隔离/去耦电路技术，其允许输入脉冲宽度在宽范围内变化。 这允许写入操作对控制脉冲宽度不敏感，从而产生有效的输入隔离方案。
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公开(公告)号：US5939898A
公开(公告)日：1999-08-17
申请号：US881265
申请日：1997-06-24
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/096 , H03K19/0966
摘要： Very fast very large scale integrated (VLSI) chips can be built-up from "self-resetting" or "self-timed" macros. An input isolator circuit provides an effective input isolation/decoupling which allows the input pulse widths to vary over a wide range. This avoids, for a large chip having many macros, a significant problem in insuring that the output from one macro is compliant with the input requirements of a receiving macro. Mixed static and dynamic circuits are used. The circuit comprises three stages. The input first stage is a static NOR circuit providing a pulse-chopping function. This first stage chops any too wide input pulse to the desired pulse width. The middle stage is a self-resetting complementary metal oxide semiconductor (SRCMOS) dynamic NOR circuit to capture input which is reset too soon. The last stage is a half-latch circuit to keep the dynamic node at constant output voltage level. The interfaces of all self-resetting macros in accordance with the teachings of the invention have no need for a handshake circuit or interlock circuits.
摘要翻译： 非常快速的非常大规模的集成（VLSI）芯片可以由“自复位”或“自定时”宏构建。 输入隔离器电路提供有效的输入隔离/去耦，其允许输入脉冲宽度在宽范围内变化。 这避免了对于具有许多宏的大芯片，确保一个宏的输出符合接收宏的输入要求的重大问题。 使用混合静态和动态电路。 该电路包括三个阶段。 输入第一级是提供脉冲切断功能的静态NOR电路。 该第一阶段将任何太宽的输入脉冲切除到期望的脉冲宽度。 中间阶段是一种自复位互补金属氧化物半导体（SRCMOS）动态NOR电路，用于捕获复位过快的输入。 最后一个阶段是将动态节点保持在恒定输出电压电平的半锁存电路。 根据本发明的教导，所有自复位宏的接口不需要握手电路或互锁电路。
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