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公开(公告)号：US5499005A
公开(公告)日：1996-03-12
申请号：US187951
申请日：1994-01-28
CPC分类号： H01P3/088 , H01P5/12 , H01F2017/004
摘要： A transmission line device (200) employs a first ground plane (118) that is disposed on a first dielectric substrate (202). A first conductive layer (210) that encloses a first area (213)is disposed on a second dielectric substrate (206), which substrate is positioned substantially adjacent to the first dielectric substrate (202). A second conductive layer (211) that encloses an area corresponding to the first area (213) is disposed on a third dielectric substrate (207), which substrate is positioned substantially adjacent to the second dielectric substrate (206). A coil structure is thereby provided that can be employed in the fabrication of a transmission line device, according to the invention.
摘要翻译： 传输线装置（200）采用设置在第一电介质基片（202）上的第一接地平面（118）。 包围第一区域（213）的第一导电层（210）设置在第二电介质基板（206）上，该基板基本上邻近第一电介质基板（202）定位。 包围对应于第一区域（213）的区域的第二导电层（211）设置在第三电介质基板（207）上，该第二介电基板（207）基本上与第二电介质基板（206）相邻。 由此可以提供根据本发明的用于制造传输线装置的线圈结构。
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2.发明授权Embedded ground plane for providing shielded layers in low volume multilayer transmission line devices 失效用于在低体积多层传输线路器件中提供屏蔽层的嵌入式接地层
公开(公告)号：US5467064A
公开(公告)日：1995-11-14
申请号：US187967
申请日：1994-01-28
申请人： Wang-Chang A. Gu
发明人： Wang-Chang A. Gu
摘要： An electrical circuit (400) includes a first input means (401) for providing an input signal, a first output means (406) for providing an output signal, and a transmission line device (405) electrically positioned between the first input means (401) and the first output means (406). The first transmission line device includes a first ground plane (409) disposed on a first dielectric substrate (402), a first conductive layer (405-1) enclosing a first area on a second dielectric substrate (403) that is positioned substantially adjacent to the first dielectric substrate (402). The transmission line device (405) further includes a second conductive layer (405-2) that encloses an area corresponding to the first area on a first major surface of a third dielectric substrate (404) that is positioned substantially adjacent to the second dielectric substrate. Lastly, an embedded ground plane (411) is disposed on a fourth dielectric substrate (412)that is positioned substantially between the second dielectric substrate (403) and the third dielectric substrate (404 ).
摘要翻译： 电路（400）包括用于提供输入信号的第一输入装置（401），用于提供输出信号的第一输出装置（406）和电气定位在第一输入装置（401）之间的传输线装置 ）和第一输出装置（406）。 第一传输线装置包括设置在第一电介质基片（402）上的第一接地平面（409），第一导电层（405-1），该第一导电层包围第二电介质基片上的第一区域， 第一电介质基板（402）。 传输线装置（405）还包括第二导电层（405-2），该第二导电层包围与第三电介质基板（404）的第一主表面上的第一区域相对应的区域，第三介电基片 。 最后，嵌入式接地平面（411）设置在基本位于第二电介质基片（403）和第三电介质基片（404）之间的第四电介质基片（412）上。
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3.发明授权公开(公告)号：US06426683B1
公开(公告)日：2002-07-30
申请号：US09436428
申请日：1999-11-09
IPC分类号： H03H712
CPC分类号： H03H9/0004 , H03H7/01 , H03H7/1758 , H03H7/1775 , H03H7/383 , H03H9/0542
摘要： An integrated filter circuit and a method of fabrication are disclosed, wherein the integrated filter has an input and an output parasitic shunt impedance. Input and output electrical components are coupled to the input and output terminals, respectively, to reduce the input and output parasitic shunt impedances. The input and output electrical components each include one of a coil, a section of transmission line, a coil and tuneable capacitance connected in a series tuned circuit, or a coil and tuneable capacitance connected in a parallel tuned circuit. The integrated filter includes input and output multilayer ceramic integrated coils which may be positioned so that capacitive coupling between the coils substantially cancels inductive coupling therebetween, and/or an interlayer gridded ground wall is positioned between the input and output coils
摘要翻译： 公开了集成滤波器电路和制造方法，其中集成滤波器具有输入和输出寄生并联阻抗。 输入和输出电气元件分别耦合到输入和输出端子，以减少输入和输出寄生并联阻抗。 输入和输出电气部件各自包括线圈，传输线的一部分，连接在串联调谐电路中的线圈和可调电容，或并联调谐电路中连接的线圈和可调电容中的一个。 集成滤波器包括输入和输出多层陶瓷集成线圈，其可以被定位成使得线圈之间的电容耦合基本上抵消它们之间的感性耦合，和/或层间格栅接地壁位于输入和输出线圈之间
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4.发明授权High efficiency power amplifier having reduced output matching networks for use in portable devices 有权具有减少的用于便携式设备的输出匹配网络的高效率功率放大器公开(公告)号：US06262629B1
公开(公告)日：2001-07-17
申请号：US09347675
申请日：1999-07-06
IPC分类号： H03F368
CPC分类号： H03F1/0288 , H03F1/0261 , H03F2200/198
摘要： A power amplifier includes a carrier amplifier path and a peaking amplifier path. The carrier amplifier path includes a carrier amplifier (208), and an impedance transforming network (214). The peaking amplifier path includes a peaking amplifier (210), an impedance transforming network (216), and a phase delay quarter wave element (226). The arrangement forms an inverted Doherty combiner where as the nominal impedance at a summing node (230) increases with increased conduction from the peaking amplifier, the load impedance at the output of the carrier amplifier decreases so as to maintain the carrier amplifier at a saturation point as the input signal (232) increases, and results in a reduction of the number of phase delay elements needed over a conventional Doherty approach. In a preferred embodiment the carrier and peaking amplifiers consist of cascaded stages, and are disposed on a common integrated circuit die (304). The impedance transforming networks and phase delay element are disposed on a common substrate (306), as is an input splitter network (308).
摘要翻译： 功率放大器包括载波放大器路径和峰化放大器路径。 载波放大器路径包括载波放大器（208）和阻抗变换网络（214）。 峰化放大器路径包括峰值放大器（210），阻抗变换网络（216）和相位延迟四分之一波长元件（226）。 该布置形成反向Doherty组合器，其中当加法节点（230）处的标称阻抗随着来自峰化放大器的传导增加而增加时，载波放大器的输出处的负载阻抗减小，以便将载波放大器保持在饱和点 随着输入信号（232）增加，并且导致相对于常规Doherty方法所需的相位延迟元件的数量的减少。 在优选实施例中，载波和峰值放大器由级联级组成，并且被布置在公共集成电路管芯（304）上。 阻抗变换网络和相位延迟元件如输入分配器网络（308）一样设置在公共基板（306）上。
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公开(公告)号：US5621366A
公开(公告)日：1997-04-15
申请号：US620630
申请日：1996-03-22
CPC分类号： H01P7/084
摘要： A high Q multi-layer ceramic transmission line resonator (100) used for RF applications. The resonator (100) includes a plurality of strips (102) which are separated by a ceramic substrate (104). Each of the strips are interconnected using vias (110) passing through the ceramic substrate (104). The invention utilizes current manufacturing processes to fabricate an equivalent thick center conductor to effectively increase the Q factor. This allows for the resonator to be used in miniature RF communication devices utilized in high tier devices such as voltage controlled oscillators (VCOs) or integrated filter circuits.
摘要翻译： 用于RF应用的高Q多层陶瓷传输线谐振器（100）。 谐振器（100）包括被陶瓷衬底（104）分隔开的多个条带（102）。 每个条带通过穿过陶瓷基板（104）的通路（110）相互连接。 本发明利用当前的制造工艺来制造等效的中心导体以有效地增加Q因子。 这允许将谐振器用于在诸如压控振荡器（VCO）或集成滤波器电路的高层设备中使用的微型RF通信设备中。
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公开(公告)号：US5426404A
公开(公告)日：1995-06-20
申请号：US189030
申请日：1994-01-28
摘要： An electrical circuit (500) includes an input means (503) for providing an input signal, an output means for providing an output signal, and a transmission line device (421) disposed substantially between the input means (503) and the output means. The transmission line device inludes a first ground plane (505) disposed on a first dielectric substrate (502), and a first conductive layer (421-1) disposed, and enclosing a first area, on a second dielectric substrate (506) that is positioned substantially adjacent to the first dielectric substrate (502). The transmission line device (421) further includes a second conductive layer (421-2) that encloses an area corresponding to the first area on a first major surface of a third dielectric substrate (504) that is positioned substantially adjacent to the second dielectric substrate (506).
摘要翻译： 电路（500）包括用于提供输入信号的输入装置（503），用于提供输出信号的输出装置和基本上设置在输入装置（503）和输出装置之间的传输线装置（421）。 传输线装置包括设置在第一电介质基板（502）上的第一接地平面（505）和在第二电介质基板（506）上设置并包围第一区域的第一导电层（421-1） 定位成基本上邻近于第一电介质基板（502）。 传输线装置（421）还包括第二导电层（421-2），该第二导电层包围与第三电介质基片（504）的第一主表面相对应的区域，第三绝缘基片 （506）。
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