公开(公告)号：US07055114B2

公开(公告)日：2006-05-30

申请号：US10681815

申请日：2003-10-08

申请人： Wayne Dervon Kever ,  Kenneth Koch, II

发明人： Wayne Dervon Kever ,  Kenneth Koch, II

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.

摘要翻译： 过程，软件和系统不对称地缩小了VLSI电路设计的布局。 由具有第一设计规则的第一制造过程定义的第一VLSI电路设计布局被不对称地缩放到由具有第二设计规则的第二制造工艺定义的第二VLSI电路设计布局。 处理第二VLSI电路设计布局的一个或多个叶单元的布局以确保符合第二设计规则。

公开(公告)号：US06265897B1

公开(公告)日：2001-07-24

申请号：US09466493

申请日：1999-12-17

申请人： Christopher Allan Poirier ,  Samuel D Naffziger ,  Wayne Dervon Kever

发明人： Christopher Allan Poirier ,  Samuel D Naffziger ,  Wayne Dervon Kever

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A pseudo-NMOS logic gate of an integrated circuit chip is enabled for a time interval that is substantially less than one-half a clock cycle of the integrated circuit. A latch responds to an output signal of the pseudo-NMOS logic gate for a period that is simultaneous with or slightly less than the time while the pseudo-NMOS logic gate is enabled. The latch derives an output signal commensurate with the output signal of the pseudo-NMOS logic gate while the pseudo-NMOS logic gate is enabled, until the next clock cycle occurs.

摘要翻译： 集成电路芯片的伪NMOS逻辑门使能的时间间隔大大小于集成电路的时钟周期的二分之一。 在伪NMOS逻辑门使能的同时或略小于时间的同时，锁存器响应伪NMOS逻辑门的输出信号。 当伪NMOS逻辑门被使能时，锁存器导出与伪NMOS逻辑门的输出信号相当的输出信号，直到下一个时钟周期发生。