-
公开(公告)号:US20110016346A1
公开(公告)日:2011-01-20
申请号:US12884164
申请日:2010-09-16
申请人: Wei-te Lee , Shin-te Yang , Wen-ming Huang
发明人: Wei-te Lee , Shin-te Yang , Wen-ming Huang
摘要: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.
摘要翻译: 本文公开了串行总线时钟频率校准系统及其方法。 该系统利用第一频率校准装置,第二频率校准装置和第三频率校准装置来共享相同的振荡器,以便对不同的频率调谐范围执行多级时钟频率分辨率校准。 这可以带来最佳的频率分辨率,大大降低系统的复杂性并节省元件成本。
-
公开(公告)号:US08407508B2
公开(公告)日:2013-03-26
申请号:US12884164
申请日:2010-09-16
申请人: Wei-te Lee , Shin-te Yang , Wen-ming Huang
发明人: Wei-te Lee , Shin-te Yang , Wen-ming Huang
IPC分类号: H03D3/24
摘要: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.
摘要翻译: 本文公开了串行总线时钟频率校准系统及其方法。 该系统利用第一频率校准装置,第二频率校准装置和第三频率校准装置来共享相同的振荡器,以便对不同的频率调谐范围执行多级时钟频率分辨率校准。 这可以带来最佳的频率分辨率,大大降低系统的复杂性并节省元件成本。
-
公开(公告)号:US08140882B2
公开(公告)日:2012-03-20
申请号:US12388373
申请日:2009-02-18
申请人: Wei-te Lee , Shin-te Yang , Yen-fah Chu
发明人: Wei-te Lee , Shin-te Yang , Yen-fah Chu
IPC分类号: H03D3/24
摘要: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.
摘要翻译: 本文公开了串行总线时钟频率校准系统及其方法。 该系统利用第一频率校准装置和第二频率校准装置来共享振荡器,以便执行用于产生不同频率调谐范围的两级时钟频率分辨率校准。 这可以带来最佳的频率分辨率,并大大降低系统复杂性并节省元件成本。
-
公开(公告)号:US20100122106A1
公开(公告)日:2010-05-13
申请号:US12388373
申请日:2009-02-18
申请人: Wei-te Lee , Shin-te Yang , Yen-fah Chu
发明人: Wei-te Lee , Shin-te Yang , Yen-fah Chu
摘要: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.
摘要翻译: 本文公开了串行总线时钟频率校准系统及其方法。 该系统利用第一频率校准装置和第二频率校准装置来共享振荡器,以便执行用于产生不同频率调谐范围的两级时钟频率分辨率校准。 这可以带来最佳的频率分辨率,并大大降低系统复杂性并节省元件成本。
-
-
-