公开(公告)号：US20060290385A1

公开(公告)日：2006-12-28

申请号：US11168718

申请日：2005-06-28

申请人： Wendy Belluomini ,  Robert Montoye ,  Aniket Saha

发明人： Wendy Belluomini ,  Robert Montoye ,  Aniket Saha

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

摘要翻译： 具有由电压非对称时钟控制的预充电元件的动态逻辑电路在动态数字电路中提供了增强的抗噪声能力。 通过对具有减小预充电元件的电压方向上的摆幅减小的信号对预充电元件进行计时，预充电元件提供小电流，防止栅极的动态求和节点由于 噪音，并且消除了对保持装置的需要。 将降频摆动非对称时钟提供为单独的信号可防止电路其余部分的性能下降。 具体地说，利用全摆动时钟来控制电路的动态部分中的脚部装置，使得评估不会受到噪声的影响或减慢。 电路的任何静态部分中的脚踏和上拉器件也可以通过全频时钟控制，从而不影响开关速度和漏电抗扰度。

公开(公告)号：US20060290382A1

公开(公告)日：2006-12-28

申请号：US11168691

申请日：2005-06-28

申请人： Wendy Belluomini ,  Aniket Saha

发明人： Wendy Belluomini ,  Aniket Saha

IPC分类号： H03K19/096

CPC分类号： H03K19/0016

摘要： A method and apparatus for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.

摘要翻译： 有限开关动态逻辑（LSDL）电路中功耗降低的方法和装置通过减少时钟功率耗散来降低功耗。 通过在评估阶段对具有降低的电压摆幅的时钟信号对LSDL门进行时钟控制，允许LSDL栅极工作，同时显着降低时钟功耗。 由于时钟功耗主导于LSDL电路，因此时钟功耗的降低导致整体电路功耗的显着降低。 通过向本地时钟缓冲器提供额外的电源轨，在多个本地时钟缓冲器产生减小的摆动时钟，该额外的电源轨响应于从本地时钟缓冲器接收到的全摆幅评估相位时钟而被本地时钟缓冲器切换到时钟分配线 全局时钟分配网络由本地时钟缓冲区。