公开(公告)号：US20060290385A1

公开(公告)日：2006-12-28

申请号：US11168718

申请日：2005-06-28

申请人： Wendy Belluomini ,  Robert Montoye ,  Aniket Saha

发明人： Wendy Belluomini ,  Robert Montoye ,  Aniket Saha

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

摘要翻译： 具有由电压非对称时钟控制的预充电元件的动态逻辑电路在动态数字电路中提供了增强的抗噪声能力。 通过对具有减小预充电元件的电压方向上的摆幅减小的信号对预充电元件进行计时，预充电元件提供小电流，防止栅极的动态求和节点由于 噪音，并且消除了对保持装置的需要。 将降频摆动非对称时钟提供为单独的信号可防止电路其余部分的性能下降。 具体地说，利用全摆动时钟来控制电路的动态部分中的脚部装置，使得评估不会受到噪声的影响或减慢。 电路的任何静态部分中的脚踏和上拉器件也可以通过全频时钟控制，从而不影响开关速度和漏电抗扰度。

公开(公告)号：US20060290382A1

公开(公告)日：2006-12-28

申请号：US11168691

申请日：2005-06-28

申请人： Wendy Belluomini ,  Aniket Saha

发明人： Wendy Belluomini ,  Aniket Saha

IPC分类号： H03K19/096

CPC分类号： H03K19/0016

摘要： A method and apparatus for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.

摘要翻译： 有限开关动态逻辑（LSDL）电路中功耗降低的方法和装置通过减少时钟功率耗散来降低功耗。 通过在评估阶段对具有降低的电压摆幅的时钟信号对LSDL门进行时钟控制，允许LSDL栅极工作，同时显着降低时钟功耗。 由于时钟功耗主导于LSDL电路，因此时钟功耗的降低导致整体电路功耗的显着降低。 通过向本地时钟缓冲器提供额外的电源轨，在多个本地时钟缓冲器产生减小的摆动时钟，该额外的电源轨响应于从本地时钟缓冲器接收到的全摆幅评估相位时钟而被本地时钟缓冲器切换到时钟分配线 全局时钟分配网络由本地时钟缓冲区。

公开(公告)号：US20050071717A1

公开(公告)日：2005-03-31

申请号：US10670832

申请日：2003-09-25

申请人： Wendy Belluomini ,  Andrew Martin ,  Chandler McDowell ,  Robert Montoye

发明人： Wendy Belluomini ,  Andrew Martin ,  Chandler McDowell ,  Robert Montoye

IPC分类号： G01R31/3185 ,  G11C29/00 ,  G01R31/28

CPC分类号： G01R31/318572 ,  G11C29/003

摘要： A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.

摘要翻译： 用于在保持元素数组的状态下操作数据的方法和系统。 过程控制器将过程数据移动通过状态保持元素数组。 单独的扫描控制器通过从组中不充足的额外状态保持元件的一组级联锁存器扫描数据来扫描状态保持元件阵列中的数据，以启用正常扫描。 仅当通过清除该下一状态保持元件的内容已经使该组中的下一状态保持元件可用时，才使用多个本地扫描时钟来移位所选择的数据量。 以这种方式，为了扫描的目的，任何给定的锁存器不是专用的主器件或从器件锁存器，而是可以作为任一个。 本发明还涉及用于从常规LSSD时钟源产生多个本地时钟的电路。

公开(公告)号：US20050102346A1

公开(公告)日：2005-05-12

申请号：US10702992

申请日：2003-11-06

申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

IPC分类号： G06F7/50 ,  G06F7/60

CPC分类号： G06F7/607

摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

摘要翻译： 一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。 进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位 前一阶段 通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟 由高阶全加器。

公开(公告)号：US20050102345A1

公开(公告)日：2005-05-12

申请号：US10702989

申请日：2003-11-06

申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

IPC分类号： G06F7/50 ,  G06F7/60

CPC分类号： G06F7/607

摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

摘要翻译： 一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。 进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。 第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。 由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。 此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

公开(公告)号：US20080010333A1

公开(公告)日：2008-01-10

申请号：US11776454

申请日：2007-07-11

申请人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

发明人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

公开(公告)号：US20070244954A1

公开(公告)日：2007-10-18

申请号：US11670357

申请日：2007-02-01

申请人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

发明人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit. The fused Booth encoder multiplexer unit, tree unit and adder unit function in a pipeline manner with the units operating on sequential data sets during a given processing cycle. The fused Booth encoder multiplexer unit may be advantageously laid out in a design of an integrated circuit chip with no gap present in the layout, which allows uniform wire length and avoids the necessity of large transistors to drive long interconnection wires.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。 融合的布尔编码器多路复用器单元，树形单元和加法器单元在给定的处理周期内以流水线方式与在顺序数据集上操作的单元进行功能。 融合布尔编码器多路复用器单元可有利地布置在集成电路芯片的设计中，布局中不存在间隙，这允许均匀的导线长度，并避免了大晶体管驱动长互连线的必要性。

公开(公告)号：US20050195042A1

公开(公告)日：2005-09-08

申请号：US10793460

申请日：2004-03-04

申请人： Wendy Belluomini ,  Andrew Martin ,  Chandler McDowell

发明人： Wendy Belluomini ,  Andrew Martin ,  Chandler McDowell

IPC分类号： H03B1/00

CPC分类号： H03K3/0315 ,  G01R31/31725

摘要： A method and ring oscillator circuit for measuring circuit delays over a wide operating range permits improved analysis of dynamic circuits. A pulse generator circuit provides a pulse to an input of a dynamic circuit under test, which may be a pre-charge or evaluation pulse that is triggered by a transition of an output of the dynamic circuit that occurs during the state opposite that of the state commanded by the pulse. The action of the circuit provides for measuring any amount of delay to the next transition in the opposite state irrespective of the pulse width. By providing a wide-range of operation, characteristics such as leakage, charge sharing, data dependent node capacitance, previous value dependence as well as other dynamic circuit behaviors may be determined. The ring oscillator circuit includes an enable start circuit that causes a first pulse to be generated by the one-shot when the ring oscillator circuit is enabled.

摘要翻译： 用于在宽工作范围内测量电路延迟的方法和环形振荡器电路允许改进动态电路的分析。 脉冲发生器电路向待测动态电路的输入端提供脉冲，该脉冲可以是在与状态相反的状态期间发生的动态电路的输出的转变触发的预充电或评估脉冲 由脉冲命令。 该电路的作用提供了在相反状态下测量下一个转换的任何延迟量，而与脉冲宽度无关。 通过提供广泛的操作，可以确定泄漏，电荷共享，数据相关节点电容，先前值依赖性以及其他动态电路行为等特征。 环形振荡器电路包括使能启动电路，当使能环形振荡器电路时，使能起始电路通过单次触发产生第一脉冲。

公开(公告)号：US07873878B2

公开(公告)日：2011-01-18

申请号：US11860461

申请日：2007-09-24

申请人： Wendy Belluomini ,  John Edward Bish ,  Kenneth Day, III ,  James Hafner ,  Bret S. Weber

发明人： Wendy Belluomini ,  John Edward Bish ,  Kenneth Day, III ,  James Hafner ,  Bret S. Weber

IPC分类号： G06F11/00

CPC分类号： G06F11/1076 ,  G06F2211/104 ,  G06F2211/109

摘要： A data storage method comprises storing first data in at least a first data chunk, wherein the first data chunk is a logical representation of one or more sectors on at least a first disk drive in a storage system; storing first metadata, associated with the first data, in at least a first appendix, wherein the first appendix is a logical representation of a sector region on at least the first disk drive in the storage system, and wherein the first metadata comprises first atomicity metadata (AMD) and first validity metadata (VMD) associated with the first data; and storing a copy of the first VMD for the first data in at least one low latency non-volatile storage (LLNVS) device.

摘要翻译： 数据存储方法包括在至少第一数据块中存储第一数据，其中第一数据块是存储系统中的至少第一磁盘驱动器上的一个或多个扇区的逻辑表示; 在至少第一附录中存储与第一数据相关联的第一元数据，其中第一附录是存储系统中的至少第一磁盘驱动器上的扇区区域的逻辑表示，并且其中第一元数据包括第一原子元数据 （AMD）和与第一数据相关联的第一有效性元数据（VMD）; 以及将第一数据的第一VMD的副本存储在至少一个低延迟非易失性存储（LLNVS）设备中。

公开(公告)号：US20090083504A1

公开(公告)日：2009-03-26

申请号：US11860461

申请日：2007-09-24

申请人： Wendy Belluomini ,  John Edward Bish ,  Kenneth Day, III ,  James Hafner ,  Bret S. Weber

发明人： Wendy Belluomini ,  John Edward Bish ,  Kenneth Day, III ,  James Hafner ,  Bret S. Weber

IPC分类号： H03M13/09 ,  G06F12/16

CPC分类号： G06F11/1076 ,  G06F2211/104 ,  G06F2211/109

摘要： A data storage method comprises storing first data in at least a first data chunk, wherein the first data chunk is a logical representation of one or more sectors on at least a first disk drive in a storage system; storing first metadata, associated with the first data, in at least a first appendix, wherein the first appendix is a logical representation of a sector region on at least the first disk drive in the storage system, and wherein the first metadata comprises first atomicity metadata (AMD) and first validity metadata (VMD) associated with the first data; and storing a copy of the first VMD for the first data in at least one low latency non-volatile storage (LLNVS) device.

摘要翻译： 数据存储方法包括在至少第一数据块中存储第一数据，其中第一数据块是存储系统中的至少第一磁盘驱动器上的一个或多个扇区的逻辑表示; 在至少第一附录中存储与第一数据相关联的第一元数据，其中第一附录是存储系统中的至少第一磁盘驱动器上的扇区区域的逻辑表示，并且其中第一元数据包括第一原子元数据 （AMD）和与第一数据相关联的第一有效性元数据（VMD）; 以及将第一数据的第一VMD的副本存储在至少一个低延迟非易失性存储（LLNVS）设备中。