公开(公告)号：US20190341120A1

公开(公告)日：2019-11-07

申请号：US15970832

申请日：2018-05-03

Applicant: Western Digital Technologies, Inc.

Inventor： Mordekhay ZEHAVI ,  Mahmud ASFUR ,  Yonatan TZAFRIR

IPC: G11C29/50 ,  G06F11/07

Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.

公开(公告)号：US20190056880A1

公开(公告)日：2019-02-21

申请号：US15679468

申请日：2017-08-17

Applicant: Western Digital Technologies, Inc.

Inventor： Yonatan TZAFRIR ,  Mordekhay ZEHAVI ,  Mahmud ASFUR

IPC: G06F3/06 ,  G06K7/00

Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

公开(公告)号：US20220058140A1

公开(公告)日：2022-02-24

申请号：US17181907

申请日：2021-02-22

Applicant: Western Digital Technologies, Inc.

Inventor： Israel ZIMMERMAN ,  Mahmud ASFUR ,  Mordekhay ZEHAVI

IPC: G06F13/16 ,  G06F11/10 ,  H03M13/11 ,  G06F16/23 ,  G06F15/80

Abstract: A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.