-
1.发明授权Creating scan chain definition from high-level model using high-level model simulation 有权使用高级模型模拟从高级模型创建扫描链定义公开(公告)号：US08281279B2
公开(公告)日：2012-10-02
申请号：US12963246
申请日：2010-12-08
CPC分类号： G01R31/318583 , G06F17/505 , G06F2217/14
摘要： Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.
摘要翻译： 提供了使用高级模型模拟从高级模型创建移位寄存器定义的机制。 机制初始化所有潜在的扫描链锁存器，识别给定扫描链中的锁存器，并将扫描链锁存器分成多个块。 对于每个块，这些机制识别块中每个位移处的锁存器。 当出现发散时，机制将隔离扫描路径锁存器。
-
2.发明申请Creating Scan Chain Definition from High-Level Model Using High-Level Model Simulation 有权使用高级模型模拟从高级模型创建扫描链定义公开(公告)号：US20120151288A1
公开(公告)日：2012-06-14
申请号：US12963246
申请日：2010-12-08
IPC分类号： G06F11/26
CPC分类号： G01R31/318583 , G06F17/505 , G06F2217/14
摘要： Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.
摘要翻译： 提供了使用高级模型模拟从高级模型创建移位寄存器定义的机制。 机制初始化所有潜在的扫描链锁存器，识别给定扫描链中的锁存器，并将扫描链锁存器分成多个块。 对于每个块，这些机制识别块中每个位移处的锁存器。 当出现发散时，机制将隔离扫描路径锁存器。
-
公开(公告)号：US5548715A
公开(公告)日：1996-08-20
申请号：US258166
申请日：1994-06-10
IPC分类号： G01R31/3183 , G01R31/28
CPC分类号： G01R31/318342
摘要： This invention teaches a system (10) and method for analyzing a fault within a model of a logic circuit. The method includes the computer executed steps of (a) building a fault model of the circuit model; (b) for each modelled fault that is determined to be untestable, (b) building a discrete node set comprised of nodes of the circuit model that are relevant to the untestable fault; and (c) outputting the discrete node set for analysis. The step of building a fault model includes a step of classifying the untestable faults into at least three categories including unobservable faults, excitation conflict faults, and reverse and forward implication (RFI) conflict faults. Faults from each of these three classifications are processed differently so as to build a relevant discrete node set for subsequent analysis.
摘要翻译： 本发明教导了用于分析逻辑电路模型内的故障的系统（10）和方法。 该方法包括以下步骤：（a）构建电路模型的故障模型; （b）对于被确定为不可测试的每个建模故障，（b）构建由与不可测故障相关的电路模型的节点组成的离散节点集; 和（c）输出用于分析的离散节点集合。 建立故障模型的步骤包括将不可测试故障分为至少三类，包括不可观察的故障，激励冲突故障以及反向和前向牵连（RFI）冲突故障。 对这三种分类中的每一种的故障进行不同的处理，以构建相关的离散节点集用于后续分析。
-
-
搜索结果
3 条记录 (耗时 0.016 秒)
