HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
    1.
    发明申请
    HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 失效
    网络通信处理器架构中的HASH处理

    公开(公告)号:US20110225168A1

    公开(公告)日:2011-09-15

    申请号:US13046719

    申请日:2011-03-12

    IPC分类号: G06F17/30

    摘要: Described embodiments provide coherent processing of hash operations of a network processor having a plurality of processing modules. A hash processor of the network processor receives hash operation requests from the plurality of processing modules. A hash table identifier and bucket index corresponding to the received hash operation request are determined. An active index list is maintained for active hash operations for each hash table identifier and bucket index. If the hash table identifier and bucket index of the received hash operation request are in the active index list, the received hash operation request is deferred until the hash table identifier and bucket index corresponding to the received hash operation request clear from the active index list. Otherwise, the active index list is updated with the hash table identifier and bucket index of the received hash operation request and the received hash operation request is processed.

    摘要翻译: 所描述的实施例提供具有多个处理模块的网络处理器的散列操作的相干处理。 网络处理器的散列处理器从多个处理模块接收散列操作请求。 确定与所接收的散列操作请求对应的哈希表标识符和桶索引。 为每个哈希表标识符和桶索引的活动散列操作维护活动索引列表。 如果接收到的散列操作请求的散列表标识符和桶索引在活动索引列表中,则接收到的散列操作请求被延迟,直到与所接收的散列操作请求对应的散列表标识符和桶索引从活动索引列表中清除。 否则,主动索引列表用哈希表标识符和接收到的散列操作请求的桶索引进行更新,并且处理接收的散列操作请求。

    Hash processing in a network communications processor architecture
    2.
    发明授权
    Hash processing in a network communications processor architecture 有权
    网络通讯处理器架构中的哈希处理

    公开(公告)号:US08539199B2

    公开(公告)日:2013-09-17

    申请号:US13046717

    申请日:2011-03-12

    IPC分类号: G06F12/08

    摘要: Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table.

    摘要翻译: 描述的实施例为具有多个处理模块和共享存储器的系统提供散列处理器。 散列处理器包括具有N个条目的描述符表,每个条目对应于散列处理器的散列表。 共享存储器中的直接映射表包括至少一个包括N个散列桶的存储器块。 直接映射表包括用于每个散列表的预定数量的散列桶。 每个哈希桶包括一个或多个哈希键和值对以及链接值。 共享内存中的内存块包括可用于分配到散列表的动态哈希桶。 当直接映射表中的哈希桶被填充超过阈值时,动态哈希桶被分配给散列表。 哈希桶中的链路值被设置为分配给哈希表的动态哈希桶的地址。

    Hash processing in a network communications processor architecture
    3.
    发明授权
    Hash processing in a network communications processor architecture 失效
    网络通讯处理器架构中的哈希处理

    公开(公告)号:US08321385B2

    公开(公告)日:2012-11-27

    申请号:US13046719

    申请日:2011-03-12

    IPC分类号: G06F7/00 G06F17/00 G06F17/30

    摘要: Described embodiments provide coherent processing of hash operations of a network processor having a plurality of processing modules. A hash processor of the network processor receives hash operation requests from the plurality of processing modules. A hash table identifier and bucket index corresponding to the received hash operation request are determined. An active index list is maintained for active hash operations for each hash table identifier and bucket index. If the hash table identifier and bucket index of the received hash operation request are in the active index list, the received hash operation request is deferred until the hash table identifier and bucket index corresponding to the received hash operation request clear from the active index list. Otherwise, the active index list is updated with the hash table identifier and bucket index of the received hash operation request and the received hash operation request is processed.

    摘要翻译: 所描述的实施例提供具有多个处理模块的网络处理器的散列操作的相干处理。 网络处理器的散列处理器从多个处理模块接收散列操作请求。 确定与所接收的散列操作请求对应的哈希表标识符和桶索引。 为每个哈希表标识符和桶索引的活动散列操作维护活动索引列表。 如果接收到的散列操作请求的散列表标识符和桶索引在活动索引列表中,则接收到的散列操作请求被延迟,直到与所接收的散列操作请求对应的散列表标识符和存储桶索引从活动索引列表中清除。 否则,主动索引列表用哈希表标识符和接收到的散列操作请求的桶索引进行更新,并且处理接收的散列操作请求。

    HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
    4.
    发明申请
    HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
    网络通信处理器架构中的HASH处理

    公开(公告)号:US20110225391A1

    公开(公告)日:2011-09-15

    申请号:US13046717

    申请日:2011-03-12

    IPC分类号: G06F12/08

    摘要: Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table.

    摘要翻译: 描述的实施例为具有多个处理模块和共享存储器的系统提供散列处理器。 散列处理器包括具有N个条目的描述符表,每个条目对应于散列处理器的散列表。 共享存储器中的直接映射表包括至少一个包括N个散列桶的存储器块。 直接映射表包括用于每个散列表的预定数量的散列桶。 每个哈希桶包括一个或多个哈希键和值对以及链接值。 共享内存中的内存块包括可用于分配到散列表的动态哈希桶。 当直接映射表中的哈希桶被填充超过阈值时,动态哈希桶被分配给散列表。 哈希桶中的链路值被设置为分配给哈希表的动态哈希桶的地址。

    CONCURRENT LINKED-LIST TRAVERSAL FOR REAL-TIME HASH PROCESSING IN MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS
    6.
    发明申请
    CONCURRENT LINKED-LIST TRAVERSAL FOR REAL-TIME HASH PROCESSING IN MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS 有权
    多核线程网络处理器实时冲洗处理的同步链接列表

    公开(公告)号:US20120158729A1

    公开(公告)日:2012-06-21

    申请号:US13403468

    申请日:2012-02-23

    IPC分类号: G06F17/30

    摘要: Described embodiments process hash operation requests of a network processor. A hash processor determines a job identifier, a corresponding hash table, and a setting of a traversal indicator for a received hash operation request that includes a desired key. The hash processor concurrently generates a read request for a first bucket of the hash table, and provides the job identifier, the key and the traversal indicator to a read return processor. The read return processor stores the key and traversal indicator in a job memory and stores, in a return memory, entries of the first bucket of the hash table. If a stored entry matches the desired key, the read return processor determines, based on the traversal indicator, whether to read a next bucket of the hash table and provides the job identifier, the matching key, and the address of the bucket containing the matching key to the hash processor.

    摘要翻译: 描述的实施例处理网络处理器的散列操作请求。 哈希处理器确定作业标识符,对应的哈希表以及包括所需密钥的接收到的散列操作请求的遍历指示符的设置。 散列处理器同时为散列表的第一个桶产生读取请求,并将该作业标识符,密钥和遍历指示符提供给读取返回处理器。 读返回处理器将密钥和遍历指示符存储在作业存储器中,并且在返回存储器中存储散列表的第一个桶的条目。 如果存储的条目与期望的密钥相匹配,则读取返回处理器根据穿越指示符确定是否读取散列表的下一个桶,并提供作业标识符,匹配关键字和包含匹配的桶的地址 哈希处理器的关键。

    Multi-threaded processing with hardware accelerators
    7.
    发明授权
    Multi-threaded processing with hardware accelerators 有权
    使用硬件加速器进行多线程处理

    公开(公告)号:US08949838B2

    公开(公告)日:2015-02-03

    申请号:US13474114

    申请日:2012-05-17

    摘要: Described embodiments process multiple threads of commands in a network processor. One or more tasks are generated corresponding to each received packet, and the tasks are provided to a packet processor module (MPP). A scheduler associates each received task with a command flow. A thread updater writes state data corresponding to the flow to a context memory. The scheduler determines an order of processing of the command flows. When a processing thread of a multi-thread processor is available, the thread updater loads, from the context memory, state data for at least one scheduled flow to one of the multi-thread processors. The multi-thread processor processes a next command of the flow based on the loaded state data. If the processed command requires operation of a co-processor module, the multi-thread processor sends a co-processor request and switches command processing from the first flow to a second flow.

    摘要翻译: 描述的实施例处理网络处理器中的多个命令线程。 对应于每个接收到的分组生成一个或多个任务,并且将任务提供给分组处理器模块(MPP)。 调度器将每个接收到的任务与命令流相关联。 线程更新器将对应于流的状态数据写入上下文存储器。 调度器确定命令流的处理顺序。 当多线程处理器的处理线程可用时,线程更新器从上下文存储器加载至少一个调度流的状态数据到多线程处理器之一。 多线程处理器基于加载的状态数据处理流的下一个命令。 如果处理的命令需要协处理器模块的操作,则多线程处理器发送协处理器请求并将命令处理从第一流切换到第二流。

    Instruction breakpoints in a multi-core, multi-thread network communications processor architecture
    8.
    发明授权
    Instruction breakpoints in a multi-core, multi-thread network communications processor architecture 有权
    指令断点在多核,多线程网络通信处理器架构中

    公开(公告)号:US08868889B2

    公开(公告)日:2014-10-21

    申请号:US12976045

    申请日:2010-12-22

    摘要: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.

    摘要翻译: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器,用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。 多线程指令引擎处理与从调度程序接收到的线程相对应的指令。 多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令,并且确定是否使能网络处理器的断点模式。 如果断点模式被使能,并且获取的指令的断点指示器被设置,则分组分类器进入断点模式。 否则,如果未设置获取的指令的断点指示符,则多线程指令引擎执行读取的指令。

    Reducing data read latency in a network communications processor architecture
    9.
    发明授权
    Reducing data read latency in a network communications processor architecture 有权
    降低网络通信处理器架构中的数据读延迟

    公开(公告)号:US08505013B2

    公开(公告)日:2013-08-06

    申请号:US12975823

    申请日:2010-12-22

    IPC分类号: G06F9/46 G06F12/06

    摘要: Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

    摘要翻译: 描述的实施例为存储在网络处理器的至少一个共享存储器中的数据提供地址转换。 网络处理器的处理模块生成与多个接收到的分组中的每一个对应的任务。 分组分类器为每个任务生成上下文,每个上下文与指令线程相关联以应用于相应的分组。 指令的第一子集被存储在所述至少一个共享存储器内的树存储器中。 指令的第二子集存储在分组分类器的多线程引擎内的高速缓存中。 多线程引擎保持与高速缓存和树存储器中的第一和第二指令子集相对应的状态指示符,并且基于状态指示符,在处理线程以在指令数和物理地址之间转换时,访问查找表 在指令的第一和第二子集中的指令。

    INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
    10.
    发明申请
    INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
    多核心,多线程网络通信处理器架构中的指导性突破

    公开(公告)号:US20110225394A1

    公开(公告)日:2011-09-15

    申请号:US12976045

    申请日:2010-12-22

    IPC分类号: G06F9/312

    摘要: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.

    摘要翻译: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器,用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。 多线程指令引擎处理与从调度程序接收到的线程相对应的指令。 多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令,并且确定是否使能网络处理器的断点模式。 如果断点模式被使能,并且获取的指令的断点指示符被设置,则分组分类器进入断点模式。 否则,如果未设置获取的指令的断点指示符,则多线程指令引擎执行读取的指令。