公开(公告)号：US20120153909A1

公开(公告)日：2012-06-21

申请号：US13213368

申请日：2011-08-19

申请人： William L. Bucossi ,  John F. Bulzacchelli ,  Mohak Chhabra ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

发明人： William L. Bucossi ,  John F. Bulzacchelli ,  Mohak Chhabra ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

IPC分类号： G05F1/10

CPC分类号： H02M3/1563 ,  H02M1/15 ,  H02M2003/1566

摘要： Voltage regulator circuits and methods implementing hybrid fast-slow passgate control circuitry are provided to minimize the ripple amplitude of a regulated voltage output. In one aspect, a voltage regulator circuit includes a comparator, a first passgate device, a second passgate device, and a bandwidth limiting control circuit. The comparator compares a reference voltage to a regulated voltage at an output node of the voltage regulator circuit and generates a first control signal on a first gate control path based on a result of the comparing. The first and second passgate devices are connected to the output node of the regulator circuit. The first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node. The bandwidth limiting control circuit has an input connected to the first gate control path and an output connected to the second passgate device. The bandwidth limiting control circuit generates a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node.

摘要翻译： 提供了实现混合快速慢门控制电路的稳压器电路和方法，以最小化稳压电压输出的纹波幅度。 在一个方面，电压调节器电路包括比较器，第一通道门，第二通道器件和带宽限制控制电路。 比较器将参考电压与调节器电路的输出节点处的调节电压进行比较，并且基于比较的结果在第一门控制路径上产生第一控制信号。 第一和第二传递门装置连接到调节器电路的输出节点。 第一传递门装置通过第一控制信号被控制在爆炸操作模式中，以向输出节点提供电流。 带宽限制控制电路具有连接到第一门控制路径的输入端和连接到第二通道门装置的输出端。 带宽限制控制电路基于第一控制信号产生第二控制信号，其中第二控制信号是第一控制信号的转换速率限制版本，并且其中第二传递门由第二控制信号控制以将电流提供给 输出节点。

公开(公告)号：US07808268B2

公开(公告)日：2010-10-05

申请号：US12178245

申请日：2008-07-23

申请人： William L. Bucossi ,  Albert A. DeBrita

发明人： William L. Bucossi ,  Albert A. DeBrita

IPC分类号： H03K17/16

CPC分类号： H03K19/017581 ,  H03K19/00369

摘要： Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

摘要翻译： 控制驱动器输出转换速率的装置，其包括具有输入信号和输出信号的驱动器电路，其中驱动电路被构造和布置以便于控制输出信号的转换速率。 具有与驱动器输出信号的期望转换时间成比例的时间延迟的延迟电路耦合到驱动器电路的输出。 第一比较器检测驱动器输出信号何时上升到指定电平，而第二比较器检测驱动器输出何时下降到第二指定电平。 相位检测器耦合到第一和第二比较器的输出以及延迟电路的输出端，用于通过调整驱动器输出转换速率对比较器输出和延迟的比较器输出的相位。

公开(公告)号：US08115508B2

公开(公告)日：2012-02-14

申请号：US12053946

申请日：2008-03-24

申请人： William L. Bucossi ,  Albert A. DeBrita

发明人： William L. Bucossi ,  Albert A. DeBrita

IPC分类号： H03K17/16

CPC分类号： H03K5/12

摘要： A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to control the slew rate of the output signal. A delay circuit is coupled to an output of the driver circuit, where the delay circuit has a delay proportional to a desired target slew rate of the driver output signal. A first comparator for detecting when the driver output signal rises through a specified level, and a second comparator for detecting when the driver output falls through a second specified level are included. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases (voltage-time relationships) of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

摘要翻译： 一种设计结构，更具体地涉及一种使驱动器输出转换速率变化最小化的设计结构。 该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括具有输入信号和输出信号的驱动器电路，其中驱动电路被构造和布置成控制输出信号的转换速率。 延迟电路耦合到驱动器电路的输出，其中延迟电路具有与驱动器输出信号的期望目标转换速率成比例的延迟。 包括用于检测驱动器输出信号何时上升到指定电平的第一比较器，以及用于检测驱动器输出何时下降到第二指定电平的第二比较器。 相位检测器耦合到第一和第二比较器的输出端和延迟电路的输出端，用于通过调整驱动器输出转换速率对比较器输出和延迟比较器输出的相位（电压 - 时间关系）。

公开(公告)号：US07432730B2

公开(公告)日：2008-10-07

申请号：US11621248

申请日：2007-01-09

申请人： William L. Bucossi ,  Albert A. DeBrita

发明人： William L. Bucossi ,  Albert A. DeBrita

IPC分类号： H03K17/16

CPC分类号： H03K19/017581 ,  H03K19/00369

摘要： Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

摘要翻译： 用于控制驱动器输出转换速率的装置和方法。 该装置包括具有输入信号和输出信号的驱动器电路，其中驱动电路被构造和布置成便于控制输出信号的转换速率。 具有与驱动器输出信号的期望转换时间成比例的时间延迟的延迟电路耦合到驱动器电路的输出。 第一比较器检测驱动器输出信号何时上升到指定电平，而第二比较器检测驱动器输出何时下降到第二指定电平。 相位检测器耦合到第一和第二比较器的输出以及延迟电路的输出端，用于通过调整驱动器输出转换速率对比较器输出和延迟的比较器输出的相位。

公开(公告)号：US06731134B1

公开(公告)日：2004-05-04

申请号：US10249311

申请日：2003-03-31

申请人： William L. Bucossi ,  Bret R. Dale ,  Darin J. Daudelin

发明人： William L. Bucossi ,  Bret R. Dale ,  Darin J. Daudelin

IPC分类号： H03K1902

CPC分类号： H03K19/09429

摘要： A driver including boost circuitry for reducing tri-state delay. Boost circuitry includes boost legs (32) and (34) having boost delay chains (38) and (40), respectively. Subcircuits (35) and (39) may include a series of inverters or other devices to delay a tri-state enable signal (EN2) or (EN2BAR) for a predetermined amount of time substantially equivalent to the time it takes for a first signal (A2) to travel from input pin A to PAD. Transient current provides a boost by discharging or charging output nodes (G1) and (G2), respectively. Boost legs (32) and (34) remain on for the length of time it takes for enable signal (EN2) or (EN2BAR) to travel through subcircuits (35) and (39). The boost increases the rate of transition of output nodes (G1) and (G2) thereby reducing the delay of tri-state signal (EN2).

摘要翻译： 一个驱动器，包括用于减少三态延迟的升压电路。 升压电路包括分别具有升压延迟链（38）和（40）的升压支脚（32）和（34）。 子电路（35）和（39）可以包括一系列逆变器或其他装置，以将三态使能信号（EN2）或（EN2BAR）延迟预定量的时间，基本上等于其对于第一信号所花费的时间 A2）从输入引脚A行进到PAD。 瞬态电流分别通过对输出节点（G1）和（G2）进行放电或充电来提供增益。 升压支脚（32）和（34）在使能信号（EN2）或（EN2BAR）穿过子电路（35）和（39）所需的时间长度内保持接通。 升压增加输出节点（G1）和（G2）的转换速率，从而减少三态信号（EN2）的延迟。

公开(公告)号：US07295044B2

公开(公告)日：2007-11-13

申请号：US11275537

申请日：2006-01-12

申请人： William L. Bucossi ,  Hongfei Wu

发明人： William L. Bucossi ,  Hongfei Wu

IPC分类号： H03K5/22

CPC分类号： G06F1/04

摘要： A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.

摘要翻译： 数字时钟产生电路（及其操作方法）。 数字时钟产生电路包括第一，第二，第三差分比较器电路。 第一差分比较器电路接收正差分时钟信号和参考电压，并产生第一输出信号。 第二差分比较器电路接收正和负差分时钟信号，并产生第二输出信号。 第三差分比较器电路接收参考电压和负差分时钟信号，并产生第三输出信号。 高电平检测电路接收第一输出信号和第三输出信号，并产生使能信号。 数字时钟发生电路还包括接收第二输出信号的锁存电路和使能信号并产生数字时钟信号。 锁存电路包括具有毛刺或抗噪声的锁存器。

公开(公告)号：US06853234B2

公开(公告)日：2005-02-08

申请号：US10250159

申请日：2003-06-09

申请人： William L. Bucossi

发明人： William L. Bucossi

IPC分类号： H03K3/012 ,  H03K3/356 ,  H03L5/00

CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K3/356182

摘要： A level shift circuit that reduces PMOS to NMOS device contention whole decreasing output rise delays. The invention includes a device, comprising: a level shift circuit for shifting a signal at a first voltage at an input node to a second voltage at an output node; a boost circuit, driven by the second voltage, for decreasing a transition time of the signal between the first and second voltage; and a trigger circuit, coupled to an input of the boost circuit, for turning off the boost circuit when the signal at the output node reaches a predetermined voltage level.

摘要翻译： 降低PMOS到NMOS器件竞争的电平移位电路整体降低输出上升延迟。 本发明包括一种装置，包括：电平移位电路，用于将输入节点处的第一电压的信号移位到输出节点处的第二电压; 由所述第二电压驱动的升压电路，用于减小所述第一和第二电压之间的所述信号的转换时间; 以及耦合到所述升压电路的输入的触发电路，用于当所述输出节点处的信号达到预定电压电平时关闭所述升压电路。