公开(公告)号：US20120153909A1

公开(公告)日：2012-06-21

申请号：US13213368

申请日：2011-08-19

申请人： William L. Bucossi ,  John F. Bulzacchelli ,  Mohak Chhabra ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

发明人： William L. Bucossi ,  John F. Bulzacchelli ,  Mohak Chhabra ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

IPC分类号： G05F1/10

CPC分类号： H02M3/1563 ,  H02M1/15 ,  H02M2003/1566

摘要： Voltage regulator circuits and methods implementing hybrid fast-slow passgate control circuitry are provided to minimize the ripple amplitude of a regulated voltage output. In one aspect, a voltage regulator circuit includes a comparator, a first passgate device, a second passgate device, and a bandwidth limiting control circuit. The comparator compares a reference voltage to a regulated voltage at an output node of the voltage regulator circuit and generates a first control signal on a first gate control path based on a result of the comparing. The first and second passgate devices are connected to the output node of the regulator circuit. The first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node. The bandwidth limiting control circuit has an input connected to the first gate control path and an output connected to the second passgate device. The bandwidth limiting control circuit generates a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node.

摘要翻译： 提供了实现混合快速慢门控制电路的稳压器电路和方法，以最小化稳压电压输出的纹波幅度。 在一个方面，电压调节器电路包括比较器，第一通道门，第二通道器件和带宽限制控制电路。 比较器将参考电压与调节器电路的输出节点处的调节电压进行比较，并且基于比较的结果在第一门控制路径上产生第一控制信号。 第一和第二传递门装置连接到调节器电路的输出节点。 第一传递门装置通过第一控制信号被控制在爆炸操作模式中，以向输出节点提供电流。 带宽限制控制电路具有连接到第一门控制路径的输入端和连接到第二通道门装置的输出端。 带宽限制控制电路基于第一控制信号产生第二控制信号，其中第二控制信号是第一控制信号的转换速率限制版本，并且其中第二传递门由第二控制信号控制以将电流提供给 输出节点。

公开(公告)号：US08841893B2

公开(公告)日：2014-09-23

申请号：US13213578

申请日：2011-08-19

申请人： John F. Bulzacchelli ,  Carrie E. Cox ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

发明人： John F. Bulzacchelli ,  Carrie E. Cox ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

IPC分类号： G05F1/575

CPC分类号： G05F1/575

摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

摘要翻译： 双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢 比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

公开(公告)号：US20120153910A1

公开(公告)日：2012-06-21

申请号：US13213578

申请日：2011-08-19

申请人： John F. Bulzacchelli ,  Carrie E. Cox ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

发明人： John F. Bulzacchelli ,  Carrie E. Cox ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

IPC分类号： G05F1/10

CPC分类号： G05F1/575

摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

摘要翻译： 双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢 比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

公开(公告)号：US07705640B2

公开(公告)日：2010-04-27

申请号：US12019748

申请日：2008-01-25

申请人： Steven M. Clements ,  Todd M. Rasmus

发明人： Steven M. Clements ,  Todd M. Rasmus

IPC分类号： H03L7/06

CPC分类号： H03L7/0895

摘要： A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.

摘要翻译： 一种用于设置电荷泵的共模电压电平以从压控振荡器（VCO）产生低占空比失真的方法，系统和电路设计产品。 差分电荷泵利用共模反馈（CMF）网络来控制共模电压电平。 来自VCO的当前饥饿延迟单元的复制电路替代共模反馈电路内的单位增益缓冲电路。 插入当前受饥饿的延迟单元复制电路允许充分的负反馈补偿，同时允许锁相环（PLL）以宽带宽工作。 作为利用来自VCO的当前饥饿延迟单元的复制电路的结果，共模电压电平被最佳地集中于与VCO的接口，从而最小化占空比失真。

公开(公告)号：US07405620B2

公开(公告)日：2008-07-29

申请号：US11458712

申请日：2006-07-20

申请人： Hayden C. Cranford, Jr. ,  Todd M. Rasmus

发明人： Hayden C. Cranford, Jr. ,  Todd M. Rasmus

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F1/52 ,  H03F2203/45352 ,  H03F2203/45481

摘要： A method of forming a differential amplifier on a substrate which has a greater tolerance for applied voltages and a chip so formed. The differential amplifier circuit on a substrate has additional transistors connected with resistors which form a voltage divider, thereby sharing the voltage stress which may be applied and accommodating enhanced capabilities for the differential amplifier.

摘要翻译： 一种在衬底上形成差分放大器的方法，该衬底对所施加的电压具有较大的容差以及如此形成的芯片。 衬底上的差分放大器电路具有与形成分压器的电阻器连接的附加晶体管，从而共享可施加的电压应力并且为差分放大器提供增强的能力。

公开(公告)号：US09110488B2

公开(公告)日：2015-08-18

申请号：US13154840

申请日：2011-06-07

申请人： Bradford L. Hunter ,  Todd M. Rasmus

发明人： Bradford L. Hunter ,  Todd M. Rasmus

IPC分类号： G05F1/00 ,  G05F1/575 ,  G05F1/565 ,  G05F1/56

CPC分类号： G05F1/575 ,  G05F1/56

摘要： A linear regulator and a method of regulating a supply voltage are provided. Embodiments include a linear regulator with a first feedback loop and a second feedback loop. The first feedback loop is characterized by a first bandwidth and a first gain. The first feedback loop includes a first amplifier characterized by an output impedance which is significantly reduced in order to maximize the bandwidth of the first feedback loop when driving the capacitance of a control input of a series pass element. The second feedback loop is characterized by a second bandwidth and a second gain. The second feedback loop includes a second amplifier that controls the current in the first amplifier in the first feedback loop.

摘要翻译： 提供线性调节器和调节电源电压的方法。 实施例包括具有第一反馈回路和第二反馈回路的线性调节器。 第一反馈回路的特征在于第一带宽和第一增益。 第一反馈回路包括第一放大器，其特征在于输出阻抗显着减小，以便在驱动串联通过元件的控制输入的电容时使第一反馈环路的带宽最大化。 第二反馈回路的特征在于第二带宽和第二增益。 第二反馈回路包括控制第一反馈回路中的第一放大器中的电流的第二放大器。

公开(公告)号：US20090189654A1

公开(公告)日：2009-07-30

申请号：US12019748

申请日：2008-01-25

申请人： Steven M. Clements ,  Todd M. Rasmus

发明人： Steven M. Clements ,  Todd M. Rasmus

IPC分类号： H03L7/06

CPC分类号： H03L7/0895

摘要： A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.

摘要翻译： 一种用于设置电荷泵的共模电压电平以从压控振荡器（VCO）产生低占空比失真的方法，系统和电路设计产品。 差分电荷泵利用共模反馈（CMF）网络来控制共模电压电平。 来自VCO的当前饥饿延迟单元的复制电路替代共模反馈电路内的单位增益缓冲电路。 插入当前受饥饿的延迟单元复制电路允许充分的负反馈补偿，同时允许锁相环（PLL）以宽带宽工作。 作为利用来自VCO的当前饥饿延迟单元的复制电路的结果，共模电压电平被最佳地集中于与VCO的接口，从而最小化占空比失真。

公开(公告)号：US07480867B1

公开(公告)日：2009-01-20

申请号：US10403427

申请日：2003-03-31

申请人： Sandra J. Racine ,  Todd M. Rasmus ,  Scott A. Jungers ,  Joann E. Jancik

发明人： Sandra J. Racine ,  Todd M. Rasmus ,  Scott A. Jungers ,  Joann E. Jancik

IPC分类号： G06F3/00

CPC分类号： G06Q10/08

摘要： A system is described that includes a host computer and a user interface module executing on a client computer. The host computer maintains data for shipment items, and the client computer executes a user interface module that presents a user interface that includes at least one activity region having a preference control input and a set of data fields to display at least a portion of the data associated with the shipment items. In response to activation of the preference control input by a user, the user interface module presents a preference control window to selectively enable and disable the inclusion of each of the data fields within the activity region.

摘要翻译： 描述了包括主计算机和在客户端计算机上执行的用户界面模块的系统。 主计算机维护用于装运物品的数据，并且客户端计算机执行用户界面模块，该用户界面模块呈现包括具有偏好控制输入和一组数据字段的至少一个活动区域的用户界面，以显示数据的至少一部分 与装运项目相关联。 响应于用户输入的偏好控制的激活，用户界面模块呈现偏好控制窗口，以选择性地启用和禁用在活动区域​​内包含每个数据字段。

公开(公告)号：US07376571B1

公开(公告)日：2008-05-20

申请号：US10403658

申请日：2003-03-31

申请人： Sandra J. Racine ,  Todd M. Rasmus ,  Scott A. Jungers ,  Joann E. Jancik

发明人： Sandra J. Racine ,  Todd M. Rasmus ,  Scott A. Jungers ,  Joann E. Jancik

IPC分类号： G06Q99/00 ,  G06F3/048

CPC分类号： G06F3/0482 ,  G06Q10/08

摘要： A logistics management system is described that includes a host computer that performs logistics management tasks for shipment items, and a user interface module that presents a user interface for the host computer. The user interface module generates a user interface having windows for performing the logistics management tasks. The user interface module generates each of the windows to include an item selection region to receive criteria for selecting one or more of items associated with the freight shipments, one or more activity regions to receive activity data for the activities, and an action input region to receive action input specifying one of the logistics management tasks. The host computing system processes the activity data captured with a single window to complete the specified logistics management task in response to the action input received from a user.

摘要翻译： 描述了一种物流管理系统，其包括执行装运物品的物流管理任务的主计算机以及呈现用于主计算机的用户界面的用户界面模块。 用户界面模块生成具有执行物流管理任务的窗口的用户界面。 用户接口模块生成每个窗口以包括项目选择区域，以接收用于选择与货物运输相关联的一个或多个项目的标准，一个或多个活动区域以接收活动的活动数据，以及动作输入区域 接收指定物流管理任务之一的动作输入。 主计算系统处理用单个窗口捕获的活动数据，以响应于从用户接收到的动作输入来完成指定的物流管理任务。

公开(公告)号：US06977558B2

公开(公告)日：2005-12-20

申请号：US10650396

申请日：2003-08-28

申请人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman ,  Todd M. Rasmus ,  Peter R. Seidel

发明人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman ,  Todd M. Rasmus ,  Peter R. Seidel

IPC分类号： H03L7/08 ,  H03L7/14

CPC分类号： H03L7/08 ,  H03L2207/06

摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.