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公开(公告)号：US6040707A
公开(公告)日：2000-03-21
申请号：US929734
申请日：1997-09-15
IPC分类号： H03K5/02 , H03K19/003 , H03K19/0175 , H03K17/16
CPC分类号： H03K19/00361
摘要： A constant slew rate amplifier has a precision internal slew rate control reference, that generates respective positive-going and negative-going voltages, associated with corresponding excursions in the input signal. These slew rate-defining voltages are decoupled from the line, making it possible to drive the line with an amplified output signal that faithfully follows the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of the capacitance of the line. In addition, the constant slew rate amplifier of the present invention is configured to minimize power dissipation during non-transitional signal conditions, while providing substantial current to rapidly drive the line from one state to another in accordance with the input signal.
摘要翻译： 恒定压摆率放大器具有精密的内部转换速率控制参考，其产生与输入信号中的相应偏移相关联的相应的正向和负向电压。 这些压摆率定义电压与线路分离，使得可以用放大的输出信号驱动线路，该放大的输出信号忠实地遵循输入信号，并符合规定的转换速率和上升/下降时间规格，而不考虑线路的电容 。 此外，本发明的恒定转换速率放大器被配置为在非过渡信号状态期间最小化功率耗散，同时提供大量电流以根据输入信号将线路从一个状态快速驱动到另一个状态。
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公开(公告)号：US07023187B2
公开(公告)日：2006-04-04
申请号：US10213766
申请日：2002-08-07
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , H02M1/36 , H02M3/1588 , H02M2001/007 , H02M2001/009 , Y02B70/1466 , Y10S323/901
摘要： A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.
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公开(公告)号：US06362665B1
公开(公告)日：2002-03-26
申请号：US09442291
申请日：1999-11-19
IPC分类号： H03B100
CPC分类号： H03K19/00315
摘要： In a bus driver circuit having a floating gate circuit for controlling voltage on the gate of the output driver and a floating well circuit for controlling voltage on the body of the output driver, the improvement comprising a well pull up circuit coupled to the output driver for applying supply voltage to the body during transmission and for applying the output of the floating gate circuit to the body during quiescence.
摘要翻译： 在具有用于控制输出驱动器的栅极上的电压的浮动栅极电路和用于控制输出驱动器的主体上的电压的浮动阱电路的总线驱动器电路中，改进包括耦合到输出驱动器的阱上拉电路， 在传输期间向身体施加电源电压并且在静止期间将浮动门电路的输出施加到身体。
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公开(公告)号：US07005924B2
公开(公告)日：2006-02-28
申请号：US10886793
申请日：2004-07-08
申请人： Sumer Can , William B. Shearon , Raymond Giordano
发明人： Sumer Can , William B. Shearon , Raymond Giordano
IPC分类号： H02H7/20
CPC分类号： H03F1/52
摘要： The current limiting circuit of the present invention includes a transconductance amplifier having two outputs and forming a conventional feedback loop. A first output connects to an output transistor and a second output is a replica output used to form a rapid response feedforward path to control the gate of the output transistor, for example, an external MOSFET.
摘要翻译： 本发明的限流电路包括具有两个输出并形成常规反馈回路的跨导放大器。 第一输出连接到输出晶体管，第二输出是用于形成快速响应前馈路径以控制输出晶体管例如外部MOSFET的栅极的复制输出。
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公开(公告)号：US06351158B1
公开(公告)日：2002-02-26
申请号：US09569894
申请日：2000-05-12
IPC分类号： H03B100
CPC分类号： H03K19/00315
摘要： A bus driver circuit has floating gate circuits with three transistors. Two of the transistors for an inverter for operating the output power transistor. The third transistor is connected to receive control signals from well pull circuits. The control signal keeps the third transistor off when the bus driver circuit is not enabled.
摘要翻译： 总线驱动电路具有三个晶体管的浮动栅极电路。 用于操作输出功率晶体管的反相器的两个晶体管。 第三晶体管被连接以从阱拉电路接收控制信号。 当总线驱动电路未使能时，控制信号保持第三个晶体管关闭。
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