-
公开(公告)号：US07489706B2
公开(公告)日：2009-02-10
申请号：US10879988
申请日：2004-06-28
申请人： William T. Hatley , Roy Liang Chua
发明人： William T. Hatley , Roy Liang Chua
IPC分类号： H04J3/06
CPC分类号： H04L43/106 , H04L43/0852
摘要： Timestamp information can be placed in a frame that includes a first portion processable at a selected layer of a protocol stack and a second portion processable at a lower protocol layer of the protocol stack subsequently to the processing of the first portion, wherein the first portion is contained within the second portion and wherein a numerically computed error detection code for the second portion is computed during processing of the second portion. A timestamp signature having a timestamp subfield of initialized data and a corrector subfield of initialized data is embedded in the first portion during processing thereof at the selected protocol layer. A numerical constant functionally equivalent to the numerically computed error detection code is determinable from the initialized data in the timestamp subfield and the corrector subfield. The data in said timestamp subfield is modified with timestamp information subsequently to processing of the second portion at the lower protocol layer. The data in the corrector subfield is then modified such that the numerical constant as determinable from the modified data in the timestamp subfield and the corrector subfield remains unchanged, whereby the numerically computed error detection code computed at the lower protocol layer remains valid.
摘要翻译： 时间戳信息可以被放置在帧中，该帧包括在协议栈的选定层处可处理的第一部分，以及随后在第一部分的处理中可在协议栈的较低协议层处理的第二部分，其中第一部分是 包含在第二部分内，并且其中在第二部分的处理期间计算用于第二部分的数字计算的检错码。 在所选择的协议层的处理期间，将具有初始化数据的时间戳子字段和初始化数据的校正子字段的时间戳签名嵌入到第一部分中。 功能上等价于数值计算的检错码的数值常数可以从时间戳子字段和校正子子字段中的初始化数据确定。 所述时间戳子字段中的数据被修改为随后在较低协议层处理第二部分的时间戳信息。 然后修正校正子字段中的数据，使得从时间戳子字段和校正子字段中的修改数据确定的数值常数保持不变，由此在较低协议层计算的数值计算的错误检测码保持有效。
-
2.发明申请METHODS AND APPARATUSES FOR GENERATING NETWORK TEST PACKETS AND PARTS OF NETWORK TEST PACKETS 有权用于生成网络测试分组和网络测试分组部件的方法和设备公开(公告)号：US20110072307A1
公开(公告)日：2011-03-24
申请号：US12563399
申请日：2009-09-21
IPC分类号： G06F11/263
CPC分类号： H04L43/50
摘要： Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.
摘要翻译： 该技术的一些方面涉及由微处理器测试分组成分的测试目的的产生，随着用于通过高速FPGA结合测试分组成分的测试分组的测试目的的产生。 该技术的一些方面涉及在诸如FPGA的可编程逻辑设备上产生包含测试分组成分的输出测试分组。 这些方面被实现为装置，方法，计算机可读介质和数据结构。
-
公开(公告)号：US20090059804A1
公开(公告)日：2009-03-05
申请号：US11899358
申请日：2007-09-05
IPC分类号： H04L12/56
CPC分类号： H04L43/50 , H04L43/087
摘要： Embodiments of the invention relate to generating simulated network traffic. In some embodiments, simulated network traffic may be generated using a specification of a sequence of frames to be transmitted from the network testing device. The specification may specify at least two frames including a first frame and a second frame. The specification may further specify a first interframe gap associated with the first frame and a second interframe gap, having a different length from the first interframe gap, associated with the second frame.In some embodiments, the specification may specify an interframe gap for each frame in the sequence of frames. This information may be used to determine the relative transmit time of each frame to be transmitted. Because the specification identifies an interframe gap for each frame in the sequence, in some embodiments, multi-frame burst network traffic may be generated.
摘要翻译： 本发明的实施例涉及生成模拟网络流量。 在一些实施例中，可以使用要从网络测试设备发送的帧序列的规范来生成模拟网络业务。 该规范可以指定包括第一帧和第二帧的至少两个帧。 该规范还可以指定与第一帧相关联的第一帧间间隔和与第二帧相关联的具有与第一帧间间隔不同的长度的第二帧间间隔。 在一些实施例中，该规范可以为帧序列中的每个帧指定帧间间隔。 该信息可以用于确定要发送的每个帧的相对发送时间。 由于该规范识别序列中每帧的帧间间隔，在一些实施例中，可以生成多帧突发网络业务。
-
公开(公告)号：US08102776B2
公开(公告)日：2012-01-24
申请号：US11899358
申请日：2007-09-05
CPC分类号： H04L43/50 , H04L43/087
摘要： Embodiments of the invention relate to generating simulated network traffic. In some embodiments, simulated network traffic may be generated using a specification of a sequence of frames to be transmitted from the network testing device. The specification may specify at least two frames including a first frame and a second frame. The specification may further specify a first interframe gap associated with the first frame and a second interframe gap, having a different length from the first interframe gap, associated with the second frame.In some embodiments, the specification may specify an interframe gap for each frame in the sequence of frames. This information may be used to determine the relative transmit time of each frame to be transmitted. Because the specification identifies an interframe gap for each frame in the sequence, in some embodiments, multi-frame burst network traffic may be generated.
摘要翻译： 本发明的实施例涉及生成模拟网络流量。 在一些实施例中，可以使用要从网络测试设备发送的帧序列的规范来生成模拟网络业务。 该规范可以指定包括第一帧和第二帧的至少两个帧。 该规范还可以指定与第一帧相关联的第一帧间间隔和与第二帧相关联的具有与第一帧间间隔不同的长度的第二帧间间隔。 在一些实施例中，该规范可以为帧序列中的每个帧指定帧间间隔。 该信息可以用于确定要发送的每个帧的相对发送时间。 由于该规范识别序列中每帧的帧间间隔，在一些实施例中，可以生成多帧突发网络业务。
-
5.发明申请Methods and Apparatuses for Generating Network Test Packets and Parts of Network Test Packets 有权用于生成网络测试包和网络测试包的部分的方法和设备公开(公告)号：US20110173498A1
公开(公告)日：2011-07-14
申请号：US13073586
申请日：2011-03-28
IPC分类号： G06F11/263
CPC分类号： H04L43/50
摘要： Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.
摘要翻译： 该技术的一些方面涉及由微处理器测试分组成分的测试目的的产生，随着用于通过高速FPGA结合测试分组成分的测试分组的测试目的的产生。 该技术的一些方面涉及在诸如FPGA的可编程逻辑设备上产生包含测试分组成分的输出测试分组。 这些方面被实现为装置，方法，计算机可读介质和数据结构。
-
6.发明授权Methods and apparatuses for enhanced transmission selection-capable simulated traffic generation 有权用于增强传输选择的模拟流量生成的方法和装置公开(公告)号：US08456999B2
公开(公告)日：2013-06-04
申请号：US13212978
申请日：2011-08-18
申请人： William T. Hatley
发明人： William T. Hatley
IPC分类号： G01R31/00
CPC分类号： H04L43/18 , H04L43/10 , H04L43/106 , H04L43/50 , H04L47/6215 , H04L47/623
摘要： Various aspects of the disclosed technology relate to the generation for test purposes of test traffic, in a manner compliant with advanced flow control.
摘要翻译： 所公开技术的各个方面涉及以测试流量的测试目的的产生，其方式符合先进的流量控制。
-
7.发明授权Methods and apparatuses for generating network test packets and parts of network test packets 有权用于生成网络测试包和网络测试包的部分的方法和设备公开(公告)号：US08310952B2
公开(公告)日：2012-11-13
申请号：US13073586
申请日：2011-03-28
IPC分类号： H04L12/26
CPC分类号： H04L43/50
摘要： Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.
摘要翻译： 该技术的一些方面涉及由微处理器测试分组成分的测试目的的产生，随着用于通过高速FPGA结合测试分组成分的测试分组的测试目的的产生。 该技术的一些方面涉及在诸如FPGA的可编程逻辑设备上产生包含测试分组成分的输出测试分组。 这些方面被实现为装置，方法，计算机可读介质和数据结构。
-
8.发明申请公开(公告)号：US20130044604A1
公开(公告)日：2013-02-21
申请号：US13212978
申请日：2011-08-18
申请人： William T. Hatley
发明人： William T. Hatley
IPC分类号： H04L12/26
CPC分类号： H04L43/18 , H04L43/10 , H04L43/106 , H04L43/50 , H04L47/6215 , H04L47/623
摘要： Various aspects of the disclosed technology relate to the generation for test purposes of test traffic, in a manner compliant with advanced flow control.
摘要翻译： 所公开技术的各个方面涉及以测试流量的测试目的的产生，其方式符合先进的流量控制。
-
9.发明授权公开(公告)号：US07869381B1
公开(公告)日：2011-01-11
申请号：US12563471
申请日：2009-09-21
IPC分类号： H04L12/26
CPC分类号： H04L43/50 , H04L41/145
摘要： Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.
-
10.发明授权公开(公告)号：US07933220B2
公开(公告)日：2011-04-26
申请号：US12563399
申请日：2009-09-21
IPC分类号： H04L12/26
CPC分类号： H04L43/50
摘要： Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.043 秒)
