公开(公告)号：US20050131809A1

公开(公告)日：2005-06-16

申请号：US10733700

申请日：2003-12-11

申请人： William Watt ,  Matthew Ackley ,  William Cornell

发明人： William Watt ,  Matthew Ackley ,  William Cornell

IPC分类号： G06Q30/00 ,  G06F17/60

CPC分类号： G06Q40/04 ,  G06Q20/10 ,  G06Q30/08 ,  G06Q40/00

摘要： A method, apparatus, and system are provided for declining auction with interest rate bidding. According to one embodiment, an interest rate may be set for a transacted financial instrument, and information regarding the financial instrument and an interest rate at which the financial instrument is offered are published via a computer network. Offers from respective bidders to transact the financial instrument may be received, via the computer network, being expressed as offered interest rates at which the bidders are willing to transact the financial instrument. On the termination of a bid receiving process, whether at least one of the offers satisfies transaction criteria, as defined by a seller of the financial instrument, may be determined. If it is determined that at least one of the offers satisfies the transaction criteria, then at least one of the offers may be identified as an accepted offer.

摘要翻译： 提供一种方法，装置和系统，用于降低利率拍卖的拍卖。 根据一个实施例，可以为交易的金融工具设定利率，并且经由计算机网络发布关于金融工具的信息和提供金融工具的利率。 可以通过计算机网络收到来自相应投标人处理金融工具的报价，表示为投标人愿意处理该金融工具的提供利率。 在投标接收过程终止时，可以确定至少一个报价是否符合由该金融工具的卖方定义的交易标准。 如果确定至少一个报价符合交易标准，那么至少一个报价可以被识别为接受的报价。

公开(公告)号：US20070219771A1

公开(公告)日：2007-09-20

申请号：US11735865

申请日：2007-04-16

申请人： Henry Verheyen ,  Paraminder Sahai ,  William Watt ,  Paul Colwill

发明人： Henry Verheyen ,  Paraminder Sahai ,  William Watt ,  Paul Colwill

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F11/261 ,  G06F17/5027

摘要： In one aspect, the present invention overcomes the limitations of the prior art by provident a logic simulation ;system that uses a VLIW simulation processor with many parallel processor elements to accelerate the simulation of synthesizable tasks but that also supports non-synthesizable tasks and/or branching. In one approach, the VLIW simulation processor is based on an architecture that does not have an on-chip instruction cache. Instead, VLIW instruction words stream in directly from a program memory and the individual processor elements are programmed continuously based on the instruction words. This also allows the efficient implementation of side-entrance jumps, where a region of code can be entered in the middle of the region rather than always requiring entrance from the top. In another aspect, non-synthesizable tasks can be efficiently handled by exception handlers.

摘要翻译： 在一个方面，本发明通过公开逻辑仿真来克服现有技术的局限性;系统使用具有多个并行处理器元件的VLIW模拟处理器来加速可合成任务的仿真，但也支持非可合成任务和/或 分枝。 在一种方法中，VLIW模拟处理器基于不具有片上指令高速缓存的架构。 相反，直接从程序存储器和各个处理器元件的VLIW指令字流被基于指令字连续编程。 这也允许有效地实施侧入口跳跃，其中可以在区域中间输入代码区域，而不是总是需要从顶部进入。 另一方面，非可合成任务可以由异常处理程序有效地处理。

公开(公告)号：US20070129926A1

公开(公告)日：2007-06-07

申请号：US11292712

申请日：2005-12-01

申请人： Henry Verheyen ,  William Watt

发明人： Henry Verheyen ,  William Watt

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/261 ,  G06F17/5022

摘要： A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation. In one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, predetermined offset to the user memory address. Thus, no address translation is required at run-time.

摘要翻译： 硬件加速模拟器包括可由模拟处理器单独访问的存储存储器和程序存储器。 程序存储器存储要执行的指令以便模拟芯片。 存储存储器用于模拟用户存储器。 由于程序存储器和存储器可由模拟处理器单独访问，因此对用户存储器的读写的仿真不会阻止程序存储器和仿真处理器之间的指令传输，从而提高了仿真速度。 在一个方面，通过向用户存储器地址添加固定的预定偏移量，将用户存储器地址映射到存储器存储器地址。 因此，在运行时不需要地址转换。

公开(公告)号：US20070073528A1

公开(公告)日：2007-03-29

申请号：US11238505

申请日：2005-09-28

申请人： William Watt ,  Henry Verheyen

发明人： William Watt ,  Henry Verheyen

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.

摘要翻译： 逻辑仿真处理器在逻辑模拟期间存储在移位寄存器中产生的中间值。 模拟处理器包括多个处理器单元和将处理器单元彼此通信地耦合的互连系统。 每个处理器单元包括可配置为至少模拟逻辑门的处理器元件和与处理器元件相关联的移位寄存器。 移位寄存器包括用于存储中间值的多个条目，并被耦合以接收处理器元件的输出。 每个处理器单元还包括一个或多个复用器，用于选择移位寄存器的条目之一作为要耦合到互连系统的输出。 每个处理器单元还可以包括用于存储来自模拟处理器的数据和将数据加载到模拟处理器的本地存储器。

公开(公告)号：US4079122A

公开(公告)日：1978-03-14

申请号：US735215

申请日：1976-10-22

申请人： Victor Conrad Richard McLoughlin ,  Roger Moreton ,  William Watt

发明人： Victor Conrad Richard McLoughlin ,  Roger Moreton ,  William Watt

IPC分类号： D01F9/22

CPC分类号： D01F9/22

摘要： A process for the production of carbon fibres is described in which a precursor fibre which is a copolymer of acrylonitrile, a chlorinated monomer, and itaconic acid containing between 2 to 20 molar parts of chlorinated comoner, between 0.5 and 5 molar parts of itaconic acid and 0 to 5 molar parts of other comonomers per 100 molar parts of acrylonitrile to a temperature in the range 200.degree.-400.degree. C while the natural shrinkage of the fibre is at least restrained followed by further heat treatment at a temperature in the range 800.degree.-3000.degree. C in a non-oxidizing atmosphere.

摘要翻译： 描述了一种生产碳纤维的方法，其中，前体纤维是丙烯腈，氯化单体和衣康酸的共聚物，其含有2-20摩尔份氯化共聚单体，0.5-5摩尔份的衣康酸和 0至5摩尔份的其它共聚单体/ 100摩尔份丙烯腈至200〜-400℃的温度，同时至少抑制纤维的自然收缩，然后在800℃的温度下进一步热处理 -3000℃，在非氧化性气氛中。

公开(公告)号：US20070150702A1

公开(公告)日：2007-06-28

申请号：US11318042

申请日：2005-12-23

申请人： Henry Verheyen ,  Raj Mathur ,  William Watt

发明人： Henry Verheyen ,  Raj Mathur ,  William Watt

IPC分类号： G06F15/00

CPC分类号： G06F15/7832 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： A processor system comprising a processor and a memory system with a high data transfer rate and low average power consumption of related I/O activity. The processor system may be disposed on a single circuit board. One embodiment of a disclosed system includes a processor system that comprises a processor device, a memory device and a circuit board. The circuit board includes a substrate, electrical contacts, and interconnection lines between the contacts. The electrical contacts of the circuit board may be coupled to electrical contacts on the processor device and the memory device. The interconnection lines communicate signals, such as data or instructions, between the electrical contacts of the memory device and the process device at least 200 billion bits per second while related input/output activity of the processor and the memory consumes an average power less than ten watts.

摘要翻译： 一种处理器系统，包括具有高数据传输速率和相关I / O活动的低平均功耗的处理器和存储器系统。 处理器系统可以设置在单个电路板上。 所公开的系统的一个实施例包括处理器系统，其包括处理器装置，存储装置和电路板。 电路板包括基板，电触点和触点之间的互连线。 电路板的电触点可以耦合到处理器装置和存储装置上的电触点。 互连线路在存储器件的电触头和处理器件之间的信号（例如数据或指令）之间传送至少200亿比特/秒，而处理器和存储器的相关输入/输出活动消耗的平均功率小于10 瓦特

公开(公告)号：US20070073999A1

公开(公告)日：2007-03-29

申请号：US11291164

申请日：2005-11-30

申请人： Henry Verheyen ,  William Watt

发明人： Henry Verheyen ,  William Watt

IPC分类号： G06F15/00

CPC分类号： G06F17/5022

摘要： A simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic operation, and a shift register for storing intermediate values generating during the logic simulation. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units can also include one or more bypass multiplexers coupled between the output of the processor element and the interconnect system, for providing a path for bypassing the shift register to provide the output of the processor element directly to the interconnect system.

摘要翻译： 模拟处理器包括多个处理器单元和将处理器单元彼此通信耦合的互连系统。 每个处理器单元包括可配置为至少模拟逻辑运算的处理器元件和用于存储在逻辑模拟期间生成的中间值的移位寄存器。 每个处理器单元还包括一个或多个复用器，用于选择移位寄存器的条目之一作为要耦合到互连系统的输出。 每个处理器单元还可以包括耦合在处理器元件的输出和互连系统之间的一个或多个旁路多路复用器，用于提供用于旁路移位寄存器以将处理器元件的输出直接提供给互连系统的路径。

公开(公告)号：US4039341A

公开(公告)日：1977-08-02

申请号：US389027

申请日：1973-08-16

申请人： George Anthony Cooper ,  Rayner Michael Mayer ,  William Watt

发明人： George Anthony Cooper ,  Rayner Michael Mayer ,  William Watt

IPC分类号： C01B31/00 ,  C04B35/83 ,  D01F9/21 ,  D01F9/22 ,  D01F9/24 ,  D01F11/12 ,  D01F11/14 ,  C01B31/02 ,  C04B35/52

CPC分类号： D01F11/14 ,  C01B31/00 ,  C04B35/83 ,  D01F11/125 ,  D01F9/21 ,  D01F9/22 ,  D01F9/24 ,  D01F9/245 ,  Y10T428/2993

摘要： A process for the production of a carbon article is provided by which a synthetic organic fibre which is capable of conversion to high strength, high modulus carbon fibre and which has been partially so converted is impregnated with a synthetic organic resin and the resin/fibre impregnate subject to a carbonization treatment in an inert atmosphere at a temperature of at least 1000.degree. C. Preferably the fibre is polyacrylonitrile which has been heated at a temperature of 200.degree. to 250.degree. C in an oxidizing atmosphere. The resin may be a phenol/formaldehyde resin, a polyvinylidene chloride resin or a polyfurfuryl alcohol resin. The process is particularly suited to the production of carbon articles in the form of fibre or rod by drawing the fibre first through the resin to impregnate it and then through a die to form the resin/fibre impregnate.

摘要翻译： 提供一种生产碳制品的方法，通过该方法可以将合成有机纤维转化为高强度，高模量碳纤维并且部分地被转化的方法被合成有机树脂浸渍，并且树脂/纤维浸渍 在惰性气氛中在至少1000℃的温度下进行碳化处理。优选地，纤维是在氧化气氛中在200℃至250℃的温度下加热的聚丙烯腈。 树脂可以是酚/甲醛树脂，聚偏二氯乙烯树脂或聚糠醇树脂。 该方法特别适用于通过将纤维首先通过树脂拉伸以浸渍其中然后通过模头以形成树脂/纤维浸渍物来生产纤维或棒形式的碳制品。

公开(公告)号：US07444276B2

公开(公告)日：2008-10-28

申请号：US11238505

申请日：2005-09-28

申请人： William Watt ,  Henry T. Verheyen

发明人： William Watt ,  Henry T. Verheyen

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.

摘要翻译： 逻辑仿真处理器在逻辑模拟期间存储在移位寄存器中产生的中间值。 模拟处理器包括多个处理器单元和将处理器单元彼此通信地耦合的互连系统。 每个处理器单元包括可配置为至少模拟逻辑门的处理器元件和与处理器元件相关联的移位寄存器。 移位寄存器包括用于存储中间值的多个条目，并被耦合以接收处理器元件的输出。 每个处理器单元还包括一个或多个复用器，用于选择移位寄存器的条目之一作为要耦合到互连系统的输出。 每个处理器单元还可以包括用于存储来自模拟处理器的数据和将数据加载到模拟处理器的本地存储器。

公开(公告)号：US20070129924A1

公开(公告)日：2007-06-07

申请号：US11296007

申请日：2005-12-06

申请人： Henry Verheyen ,  William Watt

发明人： Henry Verheyen ,  William Watt

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In one aspect, logic simulation of a design of a semiconductor chip is performed on a domain-by-domain basis (e.g., by clock domain), but storing a history of the state space of the domain during simulation. In this way, additional information beyond just the end result can be reviewed in order to debug or otherwise analyze the design.

摘要翻译： 在一个方面，半导体芯片的设计的逻辑模拟在逐个域（例如，通过时钟域）执行，但是在仿真期间存储域的状态空间的历史。 以这种方式，除了最终结果之外的其他信息可以被审查，以便调试或以其他方式分析设计。