公开(公告)号：US20080072200A1

公开(公告)日：2008-03-20

申请号：US11869316

申请日：2007-10-09

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: G06F17/50 ,  G01R25/00

CPC classification number: H03D13/004 ,  G06F17/5045

Abstract: A method and radiation hardened phase frequency detector (PFD) for implementing enhanced radiation immunity performance, and a design structure on which the subject PFD circuit resides are provided. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract translation: 一种用于实现增强的辐射抗扰度性能的方法和辐射硬化相位频率检测器（PFD），以及提供了对象PFD电路所在的设计结构。 辐射硬化相位频率检测器（PFD）包括多个功能块。 每个功能块包括提供重复输入，内部节点和输出的重复组件。 重复的组件被布置成使得当对一个节点有SEU命中并且复制的节点支持PFD的功能时。

公开(公告)号：US07362154B2

公开(公告)日：2008-04-22

申请号：US11419008

申请日：2006-05-18

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: H03K3/289

CPC classification number: H03K3/0375

Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. Therefore, a radiation hardened programmable phase frequency divider that is immune to SEU's is achieved.

Abstract translation: 用于空间应用的可编程相位分频器在CMOS技术中实现，由三个辐射硬化的D型触发器和组合逻辑电路组成，以提供允许可编程分频比从1到8的反馈控制。辐射硬化D- 类型的触发器电路被设计成即使在单次事件不正常（SEU）命中之后也能以GHz频率正常运行。 新型D型触发器电路各有两对互补输入和输出，以减轻SEU。 组合逻辑电路被设计为以这样的方式利用互补输出，使得在SEU命中之后，至多任何D型触发器的四个双重互补输入中的仅一个最多被翻转。 因此，实现了对SEU免疫的辐射硬化可编程相分频器。

公开(公告)号：US20080211558A1

公开(公告)日：2008-09-04

申请号：US12056455

申请日：2008-03-27

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: H03K3/289

CPC classification number: H03K3/0375 ,  H03K19/0033 ,  H03K23/002

Abstract: A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.

Abstract translation: 体现在机器可读介质中的设计结构包括用于设计，制造和/或测试用于空间应用的CMOS技术中实现的可编程相分频器电路的信息。 可编程相位分频器由三个辐射硬化的D型触发器和组合逻辑电路组成，以提供允许可编程分频比从1到8的反馈控制。辐射强化的D型触发器电路被设计为保持运行 即使在单次事件不适（SEU）命中之后，也可以在GHz频率下正常工作。 新型D型触发器电路各有两对互补输入和输出，以减轻SEU'S。 组合逻辑电路被设计为以这样的方式利用互补输出，使得在SEU命中之后，至多任何D型触发器的四个双重互补输入中的仅一个最多被翻转。

公开(公告)号：US07683675B2

公开(公告)日：2010-03-23

申请号：US12188238

申请日：2008-08-08

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: H03D13/00

CPC classification number: H03D13/004

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract translation: 提供了一种方法和辐射硬化相位频率检测器（PFD），用于实现增强的抗辐射性能。 辐射硬化相位频率检测器（PFD）包括多个功能块。 每个功能块包括提供重复输入，内部节点和输出的重复组件。 重复的组件被布置成使得当对一个节点有SEU命中并且复制的节点支持PFD的功能时。

公开(公告)号：US07482842B2

公开(公告)日：2009-01-27

申请号：US11532301

申请日：2006-09-15

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: G01R25/00 ,  H03D13/00

CPC classification number: H03D13/004

Abstract: A radiation hardened phase frequency detector (PFD) is provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract translation: 提供了辐射硬化相位频率检测器（PFD），用于实现增强的抗辐射性能。 辐射硬化相位频率检测器（PFD）包括多个功能块。 每个功能块包括提供重复输入，内部节点和输出的重复组件。 重复的组件被布置成使得当对一个节点有SEU命中并且复制的节点支持PFD的功能时。

公开(公告)号：US20080290903A1

公开(公告)日：2008-11-27

申请号：US12188238

申请日：2008-08-08

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: G01R25/00 ,  H03D13/00

CPC classification number: H03D13/004

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract translation: 提供了一种方法和辐射硬化相位频率检测器（PFD），用于实现增强的抗辐射性能。 辐射硬化相位频率检测器（PFD）包括多个功能块。 每个功能块包括提供重复输入，内部节点和输出的重复组件。 重复的组件被布置成使得当对一个节点有SEU命中并且复制的节点支持PFD的功能时。

公开(公告)号：US07746139B2

公开(公告)日：2010-06-29

申请号：US12056455

申请日：2008-03-27

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: H03K3/289

CPC classification number: H03K3/0375 ,  H03K19/0033 ,  H03K23/002

Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and includes a number of radiation hardened D-type flip flops. The radiation hardened D-type flip flop circuits are designed to keep running properly at GHz frequencies in the presence of single event upset (SEU) hits. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs and each consists of a master latch and a slave latch connected in tandem. The master and slave latches each consist of two latch half circuits having dual complementary inputs and outputs that are mutually interconnected in a dual interlocked cell (DICE) configuration, with the result that the D-type flip flop is immune to an SEU affecting at most one of the flip flop's four dual complementary data inputs.

Abstract translation: 用于空间应用的可编程相位分频器在CMOS技术中实现，并且包括许多辐射硬化的D型触发器。 辐射硬化的D型触发器电路设计为在存在单次事件不正常（SEU）命中的情况下，以GHz频率正常运行。 新颖的D型触发器电路每个具有两对互补的输入和输出，每一对由主锁存器和从锁存器串联连接。 主锁存器和从器件锁存器各自包括具有双重互补输入和输出的两个锁存半电路，这两个互补输入和输出以双重互锁单元（DICE）配置相互互连，结果是D型触发器免受最多影响的SEU 触发器的四个双重补充数据输入之一。

公开(公告)号：US07474134B2

公开(公告)日：2009-01-06

申请号：US11923900

申请日：2007-10-25

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: H03K21/00

CPC classification number: H03K3/0375 ,  H03K19/0033 ,  H03K23/002

Abstract: The present invention provides a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.

Abstract translation: 本发明提供了一种用于空间应用的CMOS技术实现的可编程相位分频器电路。 可编程相位分频器由三个辐射硬化的D型触发器和组合逻辑电路组成，以提供允许可编程分频比从1到8的反馈控制。辐射强化的D型触发器电路被设计为保持运行 即使在单次事件不适（SEU）命中之后，也可以在GHz频率下正常工作。 新型D型触发器电路各有两对互补输入和输出，以减轻SEU。 组合逻辑电路被设计为以这样的方式利用互补输出，使得在SEU命中之后，至多任何D型触发器的四个双重互补输入中的仅一个最多被翻转。

公开(公告)号：US20080068044A1

公开(公告)日：2008-03-20

申请号：US11532301

申请日：2006-09-15

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: H03D13/00

CPC classification number: H03D13/004

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract translation: 提供了一种方法和辐射硬化相位频率检测器（PFD），用于实现增强的抗辐射性能。 辐射硬化相位频率检测器（PFD）包括多个功能块。 每个功能块包括提供重复输入，内部节点和输出的重复组件。 重复的组件被布置成使得当对一个节点有SEU命中并且复制的节点支持PFD的功能时。

公开(公告)号：US20070268055A1

公开(公告)日：2007-11-22

申请号：US11419008

申请日：2006-05-18

Applicant: William Yeh-Yung Mo

Inventor： William Yeh-Yung Mo

IPC: H03K3/00

CPC classification number: H03K3/0375

Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. Therefore, a radiation hardened programmable phase frequency divider that is immune to SEU's is achieved.

Abstract translation: 用于空间应用的可编程相位分频器在CMOS技术中实现，由三个辐射硬化的D型触发器和组合逻辑电路组成，以提供允许可编程分频比从1到8的反馈控制。辐射硬化D- 类型的触发器电路被设计成即使在单次事件不正常（SEU）命中之后也能以GHz频率正常运行。 新型D型触发器电路各有两对互补输入和输出，以减轻SEU。 组合逻辑电路被设计为以这样的方式利用互补输出，使得在SEU命中之后，至多任何D型触发器的四个双重互补输入中的仅一个最多被翻转。 因此，实现了对SEU免疫的辐射硬化可编程相分频器。