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    Programmable synchronous clock divider
    2.
    发明授权
    Programmable synchronous clock divider 有权
    可编程同步时钟分频器

    公开(公告)号：US09490777B2

    公开(公告)日：2016-11-08

    申请号：US14617950

    申请日：2015-02-10

    Applicant: Inayat Ali ,  Puneet Dodeja ,  Sachin Jain

    Inventor： Inayat Ali ,  Puneet Dodeja ,  Sachin Jain

    IPC: H03K21/00 ,  H03K3/017 ,  H03K23/00 ,  H03K21/02 ,  H03K21/10

    CPC classification number: H03K3/017 ,  H03K5/1565 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/002

    Abstract: A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.

    Abstract translation: 从输入时钟信号产生分频时钟信号。 通过基于占空比输入的值和输入时钟信号的除法产生比较值来编程分频时钟信号的占空比。 将比较值与计数值进行比较，以生成短和长脉冲信号。 基于短脉冲信号和长脉冲信号产生分频时钟信号。 分频时钟信号的占空比根据比较值而变化。

    Structure for Radiation Hardened Programmable Phase Frequency Divider Circuit
    3.
    发明申请
    Structure for Radiation Hardened Programmable Phase Frequency Divider Circuit 失效
    辐射硬化可编程相分频电路的结构

    公开(公告)号：US20080211558A1

    公开(公告)日：2008-09-04

    申请号：US12056455

    申请日：2008-03-27

    Applicant: William Yeh-Yung Mo

    Inventor： William Yeh-Yung Mo

    IPC: H03K3/289

    CPC classification number: H03K3/0375 ,  H03K19/0033 ,  H03K23/002

    Abstract: A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.

    Abstract translation: 体现在机器可读介质中的设计结构包括用于设计，制造和/或测试用于空间应用的CMOS技术中实现的可编程相分频器电路的信息。 可编程相位分频器由三个辐射硬化的D型触发器和组合逻辑电路组成，以提供允许可编程分频比从1到8的反馈控制。辐射强化的D型触发器电路被设计为保持运行 即使在单次事件不适（SEU）命中之后，也可以在GHz频率下正常工作。 新型D型触发器电路各有两对互补输入和输出，以减轻SEU'S。 组合逻辑电路被设计为以这样的方式利用互补输出，使得在SEU命中之后，至多任何D型触发器的四个双重互补输入中的仅一个最多被翻转。

    Frequency divider
    4.
    发明授权
    Frequency divider 失效
    分频器

    公开(公告)号：US07019587B2

    公开(公告)日：2006-03-28

    申请号：US10860830

    申请日：2004-06-04

    Applicant: Oliver D. Landolt

    Inventor： Oliver D. Landolt

    IPC: H03K25/00

    CPC classification number: H03K23/002

    Abstract: A frequency divider includes a current generator, a transistor and a clock input connected in series. The transistor comprises a gate and has a threshold voltage. The connection between the current generator and the transistor constituting the output of the frequency divider. The frequency divider additionally has a controlled switch connected between the output and the gate. The switch has a control input connected to the clock input. A method for dividing frequency includes providing a current generator, a transistor and a clock input connected in series. In response to a clock pulse supplied when the output is in a high state, charge is transferred from the output to the gate to raise voltage of the gate above the threshold voltage. In response to the clock pulse supplied when the output is low, charge is transferred from the gate to the output to reduce the voltage of the gate below the threshold voltage.

    Abstract translation: 分频器包括电流发生器，晶体管和串联连接的时钟输入。 晶体管包括栅极并具有阈值电压。 电流发生器与构成分频器输出的晶体管之间的连接。 分频器还具有连接在输出和门之间的受控开关。 开关具有连接到时钟输入的控制输入。 一种频率分频方法包括提供串联连接的电流发生器，晶体管和时钟输入。 响应于当输出处于高电平状态时提供的时钟脉冲，电荷从输出传送到栅极，以将栅极的电压提高到阈值电压以上。 响应于当输出为低电平时提供的时钟脉冲，电荷从栅极传输到输出端，以将栅极的电压降低到阈值电压以下。

    Display apparatus
    5.
    发明授权
    Display apparatus 失效

    公开(公告)号：US3631460A

    公开(公告)日：1971-12-28

    申请号：US3631460D

    申请日：1970-01-07

    Applicant: CONTROL DATA CORP

    Inventor： HAASE JOHN A

    IPC: H03K17/18 ,  H03K23/00 ,  G09B13/00

    CPC classification number: H03K17/18 ,  H03K23/002

    Abstract: Display apparatus providing a visual indication of the status of bistable devices. The display apparatus also coupling the voltage generated in an inductor, as its field collapses, to utilization means whenever the breakdown voltage of devices exhibiting highimpedance characteristics prior to breakdown and low impedance thereafter is exceeded. The devices being used in connection with a ring which takes advantage of the fold-back characteristic of a commercially available voltage regulator to control pulse advance.

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