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公开(公告)号：US08214543B2
公开(公告)日：2012-07-03
申请号：US13218305
申请日：2011-08-25
IPC分类号： G06F3/00
摘要： Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.
摘要翻译： 用于控制高清晰度音频（HDA）系统的能力的系统和方法，其中系统确定诸如插件卡的可选组件是否连接到系统，然后如果可选组件是 如果可选组件连接，则不连接或将其自身配置为不同的替代配置。 在一个实施例中，系统的编解码器包括可编程处理器，其被配置为读取配置授权信息，并且如果连接到系统则从可选组件读取配置信息。 处理器还根据授权和配置信息控制HDA系统的配置和编解码器的操作。 因此，该系统可以使用相同的硬件来提供不同的特征和功能。
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公开(公告)号：US20110305354A1
公开(公告)日：2011-12-15
申请号：US13218305
申请日：2011-08-25
IPC分类号： H03F99/00
摘要： Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.
摘要翻译： 用于控制高清晰度音频（HDA）系统的能力的系统和方法，其中系统确定诸如插件卡的可选组件是否连接到系统，然后如果可选组件是 如果可选组件连接，则不连接或将其自身配置为不同的替代配置。 在一个实施例中，系统的编解码器包括可编程处理器，其被配置为读取配置授权信息，并且如果连接到系统则从可选组件读取配置信息。 处理器还根据授权和配置信息控制HDA系统的配置和编解码器的操作。 因此，该系统可以使用相同的硬件来提供不同的特征和功能。
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公开(公告)号：US08028101B2
公开(公告)日：2011-09-27
申请号：US12202361
申请日：2008-09-01
IPC分类号： G06F3/00
摘要： Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.
摘要翻译： 用于控制高清晰度音频（HDA）系统的能力的系统和方法，其中系统确定诸如插件卡的可选组件是否连接到系统，然后如果可选组件是 如果可选组件连接，则不连接或将其自身配置为不同的替代配置。 在一个实施例中，系统的编解码器包括可编程处理器，其被配置为读取配置授权信息，并且如果连接到系统则从可选组件读取配置信息。 处理器还根据授权和配置信息控制HDA系统的配置和编解码器的操作。 因此，该系统可以使用相同的硬件来提供不同的特征和功能。
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公开(公告)号：US20090063720A1
公开(公告)日：2009-03-05
申请号：US12202361
申请日：2008-09-01
摘要： Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.
摘要翻译： 用于控制高清晰度音频（HDA）系统的能力的系统和方法，其中系统确定诸如插件卡的可选组件是否连接到系统，然后如果可选组件是 如果可选组件连接，则不连接或将其自身配置为不同的替代配置。 在一个实施例中，系统的编解码器包括可编程处理器，其被配置为读取配置授权信息，并且如果连接到系统则从可选组件读取配置信息。 处理器还根据授权和配置信息控制HDA系统的配置和编解码器的操作。 因此，该系统可以使用相同的硬件来提供不同的特征和功能。
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5.发明授权Systems and methods for controlling audio volume in the processor of a high definition audio codec 失效用于控制高分辨率音频编解码器处理器中音频音量的系统和方法公开(公告)号：US08224469B2
公开(公告)日：2012-07-17
申请号：US12202355
申请日：2008-09-01
CPC分类号： H03G3/3089 , G06F3/16 , G10L15/26 , G11B20/10527 , G11B2020/10574 , H03F3/217
摘要： Systems and methods for controlling the audio volume of an audio signal in an HDA codec having a programmable processor such as a DSP, wherein the codec receives digital audio signals and audio volume control verbs over an HDA bus, and the audio volume levels associated with the audio volume control verbs are used by the processor in the generation pulse width modulated (PWM) output signals, thereby controlling the audio volume levels of the output signals. The processor may be configured to adjust non-volume parameters such as PWM deadtime, in addition to adjusting audio volume, based on the audio volume levels. The codec may be implemented in a PC or other system that implements an HDA system that includes the HDA bus and HDA codec.
摘要翻译： 用于控制具有诸如DSP的可编程处理器的HDA编解码器中的音频信号的音频音量的系统和方法，其中编解码器通过HDA总线接收数字音频信号和音频音量控制动词，以及与 音频音量控制动词由处理器在生成脉宽调制（PWM）输出信号中使用，从而控制输出信号的音频音量。 除了根据音频音量水平调整音频音量之外，处理器可以被配置为调整诸如PWM死时间之类的非体积参数。 编解码器可以在实现包括HDA总线和HDA编解码器的HDA系统的PC或其他系统中实现。
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6.发明授权Systems and methods for switching and mixing signals in a multi-channel amplifier 有权用于在多通道放大器中切换和混合信号的系统和方法公开(公告)号：US07929718B1
公开(公告)日：2011-04-19
申请号：US10843852
申请日：2004-05-12
摘要： Systems and methods for scaling the number of output channels that can be provided in an audio amplification system. In one embodiment, a digital pulse width modulation (PWM) amplification system includes multiple four-channel PWM controller chips that are interconnected to enable synchronization and transfer of digital audio data from one chip to another. Input audio signals received by each of the channels are processed by sample rate converters to generate internal audio signals that have a predetermined sample rate and format. Each of the channels is synchronized so that the internal audio signal of each channel can be processed and output by any of the other channels. The PWM controller chips are connected by a high-speed interconnect that enables the transfer of data between them. Each input audio signal can be mapped to any of the outputs and can be mixed with other input signals.
摘要翻译： 用于缩放可在音频放大系统中提供的输出通道数量的系统和方法。 在一个实施例中，数字脉宽调制（PWM）放大系统包括互连的多个四通道PWM控制器芯片，以实现数字音频数据从一个芯片到另一个芯片的同步和传输。 由每个通道接收的输入音频信号由采样率转换器处理以产生具有预定采样率和格式的内部音频信号。 每个通道被同步，使得每个通道的内部音频信号可以被任何其他通道处理和输出。 PWM控制器芯片通过高速互连连接，可以在它们之间传输数据。 每个输入音频信号可以映射到任何一个输出，并且可以与其他输入信号混合。
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7.发明申请Systems and Methods for Communication between a PC Application and the DSP in a HDA Audio Codec 审中-公开PC应用程序与HDA音频编解码器中的DSP之间的通信系统和方法公开(公告)号：US20090063828A1
公开(公告)日：2009-03-05
申请号：US12202356
申请日：2008-09-01
IPC分类号： G06F9/315
CPC分类号： G06F3/162
摘要： Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes one or more conventional HDA widgets coupled to a programmable processor such as a DSP. The codec includes a set of registers that are configured to store HDA verbs and data transmitted via the HDA bus. The programmable processor is configured to identify verbs that indicate associated information is a communication from an application executing on the CPU, read the associated information, and process the information according to the associated verbs. The information may be program instructions, parametric data, requests for information, etc.
摘要翻译： 在PC中实现的用于实现在CPU上执行的应用程序与被并入高清晰度音频（HDA）系统中的编解码器的DSP之间的通信的系统和方法，其中通过HDA总线进行通信。 在一个实施例中，HDA编解码器包括耦合到诸如DSP的可编程处理器的一个或多个常规HDA小部件。 编解码器包括一组寄存器，用于存储通过HDA总线传输的HDA动词和数据。 可编程处理器被配置为识别指示相关信息的动词是来自在CPU上执行的应用程序的通信，读取相关联的信息，以及根据相关联的动词处理信息。 该信息可以是程序指令，参数数据，信息请求等。
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8.发明申请Systems and Methods for Controlling Audio Volume in the Processor of a High Definition Audio Codec 失效用于控制高分辨率音频编解码器处理器中音频音量的系统和方法公开(公告)号：US20090062948A1
公开(公告)日：2009-03-05
申请号：US12202355
申请日：2008-09-01
IPC分类号： G06F17/00
CPC分类号： H03G3/3089 , G06F3/16 , G10L15/26 , G11B20/10527 , G11B2020/10574 , H03F3/217
摘要： Systems and methods for controlling the audio volume of an audio signal in an HDA codec having a programmable processor such as a DSP, wherein the codec receives digital audio signals and audio volume control verbs over an HDA bus, and the audio volume levels associated with the audio volume control verbs are used by the processor in the generation pulse width modulated (PWM) output signals, thereby controlling the audio volume levels of the output signals. The processor may be configured to adjust non-volume parameters such as PWM deadtime, in addition to adjusting audio volume, based on the audio volume levels. The codec may be implemented in a PC or other system that implements an HDA system that includes the HDA bus and HDA codec.
摘要翻译： 用于控制具有诸如DSP的可编程处理器的HDA编解码器中的音频信号的音频音量的系统和方法，其中编解码器通过HDA总线接收数字音频信号和音频音量控制动词，以及与 音频音量控制动词由处理器在生成脉宽调制（PWM）输出信号中使用，从而控制输出信号的音频音量。 除了根据音频音量水平调整音频音量之外，处理器可以被配置为调整诸如PWM死时间之类的非体积参数。 编解码器可以在实现包括HDA总线和HDA编解码器的HDA系统的PC或其他系统中实现。
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9.发明授权System for effecting communications between a computing device and a plurality of peripheral devices 失效用于实现计算设备和多个外围设备之间的通信的系统
公开(公告)号：US5862375A
公开(公告)日：1999-01-19
申请号：US622574
申请日：1996-03-25
申请人： Douglas D. Gephardt
发明人： Douglas D. Gephardt
CPC分类号： G06F13/4221 , G06F12/0684 , G06F13/22 , G06F13/4226
摘要： A system for effecting communications between a computing device and a plurality of peripheral devices which comprises a bus controller for controlling the communications, a plurality of feedback generator circuits for providing operational status information, each of the plurality of peripheral devices having an associated one of the plurality of feedback generator circuits. The system further comprises a bus for conveying signals between the bus controller and the plurality of peripheral devices. In the preferred embodiment, each of the plurality of peripheral devices has a respective address and each of the plurality of feedback generator circuits contains the operational status information for its respective peripheral device. The bus controller interrogates the plurality of peripheral devices, each of which causes its respective feedback generator circuit to respond to such interrogation by communicating its respective operational status information to the bus controller when a respective of the peripheral devices indicates that such information is to be passed.
摘要翻译： 一种用于实现计算设备和多个外围设备之间的通信的系统，其包括用于控制通信的总线控制器，用于提供操作状态信息的多个反馈发生器电路，所述多个外围设备中的每一个具有相关联的一个 多个反馈发生器电路。 该系统还包括用于在总线控制器和多个外围设备之间传送信号的总线。 在优选实施例中，多个外围设备中的每一个具有相应的地址，并且多个反馈发生器电路中的每一个包含用于其各个外围设备的操作状态信息。 总线控制器询问多个外围设备，当各个外围设备指示这样的信息将被传递时，每个外围设备使每个外部设备使其各自的反馈发生器电路响应于这种询问，通过将其相应的操作状态信息传送到总线控制器 。
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10.发明授权
公开(公告)号：US5768584A
公开(公告)日：1998-06-16
申请号：US710047
申请日：1996-09-10
CPC分类号： G06F9/4401 , G06F12/0653
摘要： A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allows the system to power-up and execute the boot code before the array configurations are selected by firmware. In one embodiment, a memory controller includes four chip enable output lines for selectively enabling a plurality of ROM banks. One of the ROM banks includes boot code that is executed by the system microprocessor during system boot. If the user requires a ROM array consisting of four ROM banks, a separate chip enable output line is connected to each ROM bank. If the user instead requires a ROM array consisting of, for example, eight ROM banks, an external decoder may be connected to the four chip enable output lines. In this configuration, each output line of the decoder is coupled to a respective bank enable input line of the ROM banks. In either configuration, the chip enable lines are driven in a mutually exclusive relationship during system boot to access the boot code (stored within one of the ROM banks). Subsequently, the encoding of the chip enable signals at the chip enable output lines of the memory controller is dependent upon configuration information stored in a configuration register.
摘要翻译： 非易失性存储器芯片使能编码方法允许在公共存储器阵列中存储引导代码和用户应用软件。 芯片使能编码方法还允许在非易失性存储器阵列内提供可变数量的存储体，并且在固件选择阵列配置之前允许系统上电并执行引导代码。 在一个实施例中，存储器控制器包括用于选择性地启用多个ROM组的四个芯片使能输出线。 其中一个ROM库包括在系统引导期间由系统微处理器执行的引导代码。 如果用户需要由四个ROM组组成的ROM阵列，则每个ROM组连接有单独的芯片使能输出线。 如果用户需要由例如八个ROM组组成的ROM阵列，则外部解码器可以连接到四个芯片使能输出线。 在该配置中，解码器的每个输出线耦合到ROM组的相应的bank使能输入线。 在任一配置中，芯片使能线在系统引导期间以相互排斥的关系被驱动以访问引导代码（存储在ROM库之一内）。 随后，存储器控制器的芯片使能输出线处的芯片使能信号的编码取决于存储在配置寄存器中的配置信息。
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