公开(公告)号：US20200301722A1

公开(公告)日：2020-09-24

申请号：US16362122

申请日：2019-03-22

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li ,  Yue Zha

IPC: G06F9/455 ,  G06F9/50 ,  G06F17/50 ,  G06F9/54 ,  G06F12/10

Abstract: A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.

公开(公告)号：US10963302B2

公开(公告)日：2021-03-30

申请号：US16362122

申请日：2019-03-22

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li ,  Yue Zha

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/455 ,  G06F9/54 ,  G06F12/10 ,  G06F30/34

Abstract: A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.