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    COMPUTER ARCHITECTURE USING COMPUTE/STORAGE TILES
    3.
    发明申请
    COMPUTER ARCHITECTURE USING COMPUTE/STORAGE TILES 有权
    使用计算机/存储平台的计算机架构

    公开(公告)号：US20160336050A1

    公开(公告)日：2016-11-17

    申请号：US14709017

    申请日：2015-05-11

    Applicant: Wisconsin Alumni Research Foundation

    Inventor： Jing Li

    IPC: G11C7/10 ,  G11C5/06 ,  G06F13/40

    CPC classification number: G11C7/10 ,  G06F13/4022 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/14 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/0021 ,  G11C15/046 ,  G11C2207/005 ,  G11C2213/77

    Abstract: A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory elements to be used as local memories (including content addressable memories or random access memories), logic elements or interconnect elements. The ability to dynamically change the function of any of these tiles allows tight integration of memory and logic tailored to particular calculation problems reducing costs in data transfer.

    Abstract translation: 计算机体系结构采用多个互通瓦片，每个保持一组存储器元件。 可编程解码电路允许这些存储器元件用作本地存储器（包括内容寻址存储器或随机存取存储器），逻辑元件或互连元件。 动态改变任何这些瓦片功能的能力允许紧密集成存储器和逻辑，以适应特定的计算问题，从而降低数据传输中的成本。

    Spatially Programmed Logic Array Architecture
    4.
    发明申请
    Spatially Programmed Logic Array Architecture 审中-公开

    公开(公告)号：US20200301722A1

    公开(公告)日：2020-09-24

    申请号：US16362122

    申请日：2019-03-22

    Applicant: Wisconsin Alumni Research Foundation

    Inventor： Jing Li ,  Yue Zha

    IPC: G06F9/455 ,  G06F9/50 ,  G06F17/50 ,  G06F9/54 ,  G06F12/10

    Abstract: A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.

    Spatially programmed logic array architecture
    7.
    发明授权
    Spatially programmed logic array architecture 有权

    公开(公告)号：US10963302B2

    公开(公告)日：2021-03-30

    申请号：US16362122

    申请日：2019-03-22

    Applicant: Wisconsin Alumni Research Foundation

    Inventor： Jing Li ,  Yue Zha

    IPC: G06F9/50 ,  G06F9/48 ,  G06F9/455 ,  G06F9/54 ,  G06F12/10 ,  G06F30/34

    Abstract: A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.

    Computer architecture for high-speed, graph-traversal
    8.
    发明授权
    Computer architecture for high-speed, graph-traversal 有权

    公开(公告)号：US10747433B2

    公开(公告)日：2020-08-18

    申请号：US15901376

    申请日：2018-02-21

    Applicant: Wisconsin Alumni Research Foundation

    Inventor： Jing Li ,  Jialiang Zhang

    IPC: G06F16/00 ,  G06F3/06 ,  G06F16/901 ,  H03M7/40 ,  H03M7/30

    Abstract: A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.

    High density content addressable memory
    10.
    发明授权
    High density content addressable memory 有权

    公开(公告)号：US09979649B2

    公开(公告)日：2018-05-22

    申请号：US14959614

    申请日：2015-12-04

    Applicant: Wisconsin Alumni Research Foundation

    Inventor： Jing Li

    IPC: G11C8/10 ,  H04L12/743 ,  G06F13/28 ,  G06F13/16

    CPC classification number: H04L45/7457 ,  G06F13/1636 ,  G06F13/287 ,  G11C8/10

    Abstract: An associative memory that can be integrated with standard computer memory flexibly reduces its parallelism to match the memory bus speed thereby providing substantial increases in memory density possible by a multiplexing of sense amplifiers that otherwise dominate the memory structure. Apparent parallel operation is provided by an accumulator that reassembles the multiplex data. Higher memory density makes dual use of the associative memory as a content addressable memory and random-access memory possible.

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