公开(公告)号：US07655554B2

公开(公告)日：2010-02-02

申请号：US12135008

申请日：2008-06-06

申请人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

发明人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808

摘要： Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

摘要翻译： 使用通孔插头消除负载效应的方法。 根据一个实施例，本发明提供了一种处理集成电路的方法，其中减小了负载效应。 该方法包括提供基板的步骤，其特征在于第一厚度。 该方法还包括用于形成覆盖基板的金属间介电层的停止。 金属间介电层的特征在于第二厚度。 该方法还包括用于形成覆盖金属间介电层的第一光致抗蚀剂层的步骤。 第一光致抗蚀剂层与第一图案相关联。 另外，该方法包括用于形成至少部分地位于金属间介电层内部的第一开口的步骤。 第一通孔开口的特征在于第一深度。 该方法还包括用于去除第一光致抗蚀剂层的步骤。 该方法还包括形成通孔塞的步骤。

公开(公告)号：US20080308944A1

公开(公告)日：2008-12-18

申请号：US12135008

申请日：2008-06-06

申请人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

发明人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76808

摘要： Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

摘要翻译： 使用通孔插头消除负载效应的方法。 根据一个实施例，本发明提供了一种处理集成电路的方法，其中减小了负载效应。 该方法包括提供基板的步骤，其特征在于第一厚度。 该方法还包括用于形成覆盖基板的金属间介电层的停止。 金属间介电层的特征在于第二厚度。 该方法还包括用于形成覆盖金属间介电层的第一光致抗蚀剂层的步骤。 第一光致抗蚀剂层与第一图案相关联。 另外，该方法包括用于形成至少部分地位于金属间介电层内部的第一开口的步骤。 第一通孔开口的特征在于第一深度。 该方法还包括用于去除第一光致抗蚀剂层的步骤。 该方法还包括形成通孔塞的步骤。

公开(公告)号：US20100133702A1

公开(公告)日：2010-06-03

申请号：US12637704

申请日：2009-12-14

申请人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

发明人： Wu XiangHui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76808

摘要： Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

摘要翻译： 使用通孔插头消除负载效应的方法。 根据一个实施例，本发明提供了一种处理集成电路的方法，其中减小了负载效应。 该方法包括提供基板的步骤，其特征在于第一厚度。 该方法还包括用于形成覆盖基板的金属间介电层的停止。 金属间介电层的特征在于第二厚度。 该方法还包括用于形成覆盖金属间介电层的第一光致抗蚀剂层的步骤。 第一光致抗蚀剂层与第一图案相关联。 另外，该方法包括用于形成至少部分地位于金属间介电层内部的第一开口的步骤。 第一通孔开口的特征在于第一深度。 该方法还包括用于去除第一光致抗蚀剂层的步骤。 该方法还包括形成通孔塞的步骤。

公开(公告)号：US08089153B2

公开(公告)日：2012-01-03

申请号：US12637704

申请日：2009-12-14

申请人： Wu Xiang Hui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

发明人： Wu Xiang Hui ,  Ching-Tien Ma ,  Man Hua Shen ,  Chi Yu Shan

IPC分类号： H01L23/48

CPC分类号： H01L21/76808

摘要： Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

摘要翻译： 使用通孔插头消除负载效应的方法。 根据一个实施例，本发明提供了一种处理集成电路的方法，其中减小了负载效应。 该方法包括提供基板的步骤，其特征在于第一厚度。 该方法还包括用于形成覆盖基板的金属间介电层的停止。 金属间介电层的特征在于第二厚度。 该方法还包括用于形成覆盖金属间介电层的第一光致抗蚀剂层的步骤。 第一光致抗蚀剂层与第一图案相关联。 另外，该方法包括用于形成至少部分地位于金属间介电层内部的第一开口的步骤。 第一通孔开口的特征在于第一深度。 该方法还包括用于去除第一光致抗蚀剂层的步骤。 该方法还包括形成通孔塞的步骤。