公开(公告)号：US10811084B2

公开(公告)日：2020-10-20

申请号：US16376462

申请日：2019-04-05

申请人： XENERGIC AB

发明人： Babak Mohammadi ,  Joachim Neves Rodrigues

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/12 ,  G11C8/10 ,  G11C8/14 ,  G11C11/418

摘要： The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

公开(公告)号：US20230018727A1

公开(公告)日：2023-01-19

申请号：US17933933

申请日：2022-09-21

申请人： XENERGIC AB

发明人： Babak Mohammadi ,  Joachim Neves Rodrigues

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C8/10 ,  G11C8/14

摘要： The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

公开(公告)号：US11462262B2

公开(公告)日：2022-10-04

申请号：US17062283

申请日：2020-10-02

申请人： XENERGIC AB

发明人： Babak Mohammadi ,  Joachim Neves Rodrigues

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/12 ,  G11C8/10 ,  G11C8/14 ,  G11C11/418

摘要： The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

公开(公告)号：US20210035626A1

公开(公告)日：2021-02-04

申请号：US17062283

申请日：2020-10-02

申请人： XENERGIC AB

发明人： Babak Mohammadi ,  Joachim Neves Rodrigues

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/12 ,  G11C8/10 ,  G11C8/14 ,  G11C11/418

摘要： The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

公开(公告)号：US20190304535A1

公开(公告)日：2019-10-03

申请号：US16376462

申请日：2019-04-05

申请人： XENERGIC AB

发明人： Babak Mohammadi ,  Joachim Neves Rodrigues

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C11/418

摘要： The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.