公开(公告)号：US20230089431A1

公开(公告)日：2023-03-23

申请号：US17873002

申请日：2022-07-25

Applicant: XILINX, INC.

Inventor： Ronan Sean CASEY ,  Lokesh RAJENDRAN ,  Declan CAREY ,  Kevin ZHENG ,  Catherine HEARNE ,  Hongtao ZHANG

IPC: H04L25/49 ,  H04L27/04

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

公开(公告)号：US20220231889A1

公开(公告)日：2022-07-21

申请号：US17665477

申请日：2022-02-04

Applicant: XILINX, INC.

Inventor： Hongtao ZHANG ,  Winson LIN ,  Arianne ROLDAN ,  Yohan FRANS ,  Geoff ZHANG

IPC: H04L25/03 ,  H03L7/089 ,  H04L27/01

Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

公开(公告)号：US20230179216A1

公开(公告)日：2023-06-08

申请号：US17643349

申请日：2021-12-08

Applicant: XILINX, INC.

Inventor： Hao-Wei HUNG ,  Tan Kee HIAN ,  Siok Wei LIM ,  Hongtao ZHANG

IPC: H03M1/10

CPC classification number: H03M1/1023

Abstract: A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second data signal and the offset voltage and generates a first error signal based on one or more of the second data signal and the offset voltage. The control circuitry receives the first error signal and generates a first control signal indicating an adjustment to the clock signals.