公开(公告)号：US20230188314A1

公开(公告)日：2023-06-15

申请号：US17644066

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Shaojun MA ,  Chi Fung POON ,  Kevin ZHENG ,  Parag UPADHYAYA

IPC: H04L7/00 ,  H03K19/21

CPC classification number: H04L7/0037 ,  H03K19/21

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

公开(公告)号：US20230115601A1

公开(公告)日：2023-04-13

申请号：US17449293

申请日：2021-09-29

Applicant: XILINX, INC.

Inventor： Kai-An HSIEH ,  Tan Kee HIAN ,  Kevin ZHENG

IPC: H03M1/06

Abstract: Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first terminal connected to the non-inverting input and a second terminal selectively connected to a first voltage potential and a second voltage potential. The first voltage potential is greater than the second voltage potential. The SAR circuitry is connected to the output and the first capacitor network, and connects, during a first period, the second terminal of the first capacitor to the second voltage potential. The non-inverting input and the inverting input are connected to the differential voltage signal during the first period.

公开(公告)号：US20230089431A1

公开(公告)日：2023-03-23

申请号：US17873002

申请日：2022-07-25

Applicant: XILINX, INC.

Inventor： Ronan Sean CASEY ,  Lokesh RAJENDRAN ,  Declan CAREY ,  Kevin ZHENG ,  Catherine HEARNE ,  Hongtao ZHANG

IPC: H04L25/49 ,  H04L27/04

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

公开(公告)号：US20230198562A1

公开(公告)日：2023-06-22

申请号：US17559592

申请日：2021-12-22

Applicant: XILINX, INC.

Inventor： Chi Fung POON ,  Chuen-Huei CHOU ,  Weerachai NEERANARTVONG ,  Kevin ZHENG

IPC: H04B1/04 ,  H03M1/74 ,  H03M1/66

CPC classification number: H04B1/0483 ,  H03M1/74 ,  H03M1/662

Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

公开(公告)号：US20210288590A1

公开(公告)日：2021-09-16

申请号：US16814626

申请日：2020-03-10

Applicant: XILINX, INC.

Inventor： Junho CHO ,  Kevin ZHENG ,  Parag UPADHYAYA

IPC: H02M7/483

Abstract: An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.