公开(公告)号：US12045502B1

公开(公告)日：2024-07-23

申请号：US17356248

申请日：2021-06-23

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Jonathan Jasper ,  Martin Newman

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory controller includes transaction queue circuitry, a first skip event, a second skip event, a third skip event, and scheduler circuitry. The transaction queue circuitry is configured to store a first transaction, a second transaction, and a third transaction. The first transaction received is by the transaction queue circuitry before the second transaction and the third transaction. The second transaction is received by the transaction queue circuitry before the third transaction. The first skip event counter is associated with the first transaction. The second skip event counter is associated with the second transaction. The third skip event counter is associated with the third transaction. The scheduler circuitry is configured to select the third transaction before selecting the first transaction, increase a value of the first skip event counter based on selecting the third transaction before the first transaction, and communicate the third transaction to a memory device.