Optical filter having a tapered profile

    公开(公告)号:US11668874B1

    公开(公告)日:2023-06-06

    申请号:US17700077

    申请日:2022-03-21

    申请人: XILINX, INC.

    IPC分类号: G02B6/12 G02B6/293

    摘要: Disclosed herein is an optical filter configured for wavelength division and multiplexing capable of transmitting and receiving signals. The optical filter includes an optical waveguide configured to receive at an input multiple signals with different wavelengths. The optical filter includes a plurality of channels coupled at different locations along a length of the optical waveguide. Each of the plurality of channels is configured to transmit a respective one of the multiple signals. A number of ring filter stages in a first channel of the plurality of channels that is closer to the input of the optical waveguide is greater than a second channel in the plurality of channels further away from the input of the optical waveguide.

    In-package passive inductive element for reflection mitigation

    公开(公告)号:US11735519B2

    公开(公告)日:2023-08-22

    申请号:US17357087

    申请日:2021-06-24

    申请人: XILINX, INC.

    IPC分类号: H01L23/522 H01Q1/22

    摘要: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

    Reduced power and area efficient receiver circuitry

    公开(公告)号:US11575497B2

    公开(公告)日:2023-02-07

    申请号:US17351028

    申请日:2021-06-17

    申请人: XILINX, INC.

    IPC分类号: H04L7/00 H04B1/16

    摘要: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.