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公开(公告)号:US20240265857A1
公开(公告)日:2024-08-08
申请号:US18634136
申请日:2024-04-12
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Yong YUAN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0245 , G09G2320/0209 , G09G2330/021
Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. In at least one stage of a working process of the display panel, the light-emitting element in the first display region works in a first brightness mode, the light-emitting element in the second display region works in a second brightness mode, brightness in the first brightness mode is L1, and brightness in the second brightness mode is L2, where L1≠L2
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公开(公告)号:US20240071291A1
公开(公告)日:2024-02-29
申请号:US18090103
申请日:2022-12-28
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Yong YUAN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2300/0819 , G09G2300/0842 , G09G2340/0435
Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit including a driving transistor and a preset module, a light-emitting element and a gating module. A first terminal of the preset module is connected to the driving transistor, and a second terminal of the preset module is connected to a preset signal terminal or the driving transistor, a control terminal of the preset module is connected to a control signal line, a control terminal of the gating module is connected to a gating signal line configured for receiving a gating signal, the gating module is connected between the control terminal of the preset module and the control signal line, or between the first terminal of the preset module and the driving transistor, or between the second terminal of the preset module and the preset signal terminal or the driving transistor.
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公开(公告)号:US20240386840A1
公开(公告)日:2024-11-21
申请号:US18786126
申请日:2024-07-26
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Qingjun LAI , Chengxu LI , Xiangyuan LI , Jinjin YANG , Yong YUAN
Abstract: A display panel includes a driver circuit including shift registers with N stages and being cascade with each other, where N≥2, and each shift register includes a first control portion and a second control portion. The first control portion is configured to control a first output signal, where the first output signal of an i-th stage of shift register is an input signal of a j-th stage of shift register, and 1≤i≤N, 1≤j≤N. The second control portion is configured to receive at least the first output signal and a frequency control signal and control a second output signal. In a case where the first output signal is an effective pulse and a time period of the effective pulse is within a time period of an effective pulse of the frequency control signal, the second output signal is the effective pulse.
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公开(公告)号:US20240349556A1
公开(公告)日:2024-10-17
申请号:US18751342
申请日:2024-06-24
Applicant: XIAMEN TIANMA DISPLAY TECHNOLOGY CO., LTD.
Inventor: Yong YUAN
IPC: H10K59/131
CPC classification number: H10K59/131
Abstract: A display substrate, a display panel and a display device are provided. The display substrate is divided into a display region and a non-display region at least partially surrounding the display region. The display substrate includes data cables and adapter cables arranged in the display region, and connecting cables arranged in the non-display region. A part of the connecting cables are electrically connected to a part of the data cables through the adapter cables, and the remaining connecting cables are electrically connected to the remaining data cables directly. The data cables and the connecting cables are both arranged in the first direction. The data cables are arranged in a same sequence as the connecting cables electrically connected to the data cables. Therefore, performance of the display can be optimized.
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公开(公告)号:US20240265856A1
公开(公告)日:2024-08-08
申请号:US18633909
申请日:2024-04-12
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Yong YUAN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0245 , G09G2320/0209 , G09G2330/021
Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. The pixel circuit includes a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor, where a control terminal of a first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of a first presetting module in the second pixel circuit is configured to receive a second control signal.
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公开(公告)号:US20230178010A1
公开(公告)日:2023-06-08
申请号:US18103791
申请日:2023-01-31
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Yong YUAN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0245 , G09G2330/021 , G09G2320/0209
Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. The pixel circuit includes a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor, where a control terminal of a first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of a first presetting module in the second pixel circuit is configured to receive a second control signal.
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公开(公告)号:US20240347006A1
公开(公告)日:2024-10-17
申请号:US18757365
申请日:2024-06-27
Applicant: Xiamen Tianma Display Technology Co., Ltd.
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2320/0247 , G09G2340/0435
Abstract: Provided are a display panel. When a bias adjustment control signal is an effective pulse signal, a bias adjustment module is on and provides a bias adjustment signal for a drive transistor. The data refresh rate of a first pixel circuit is a first frequency F1. The data refresh rate of a second pixel circuit is a second frequency F2. F1≠F2. A data refresh period of the first pixel circuit includes R1 image refresh frames. A data refresh period of the second pixel circuit includes R2 image refresh frames. The sum of time durations of effective pulses of the bias adjustment control signal is Ws1 in the data refresh period of the first pixel circuit. The sum of time durations of effective pulses of the bias adjustment control signal is Ws2 in the data refresh period of the second pixel circuit. Ws1/R1≠Ws2/R2.
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公开(公告)号:US20240233627A1
公开(公告)日:2024-07-11
申请号:US18615222
申请日:2024-03-25
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Yong YUAN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2300/0819 , G09G2300/0842 , G09G2340/0435
Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit including a driving transistor and a preset module, a light-emitting element, a driving circuit, and a gating module. A first terminal of the preset module is connected to the driving transistor, a second terminal of the preset module is connected to a preset signal terminal or the driving transistor, a control terminal of the preset module is connected to a control signal line, and the control signal line is configured to receive a control signal. The driving circuit is configured to provide the control signal for the control signal line. The gating module is connected between the control terminal of the preset module and the driving circuit. The gating module is connected to a gating signal line, and the gating signal line is configured to receive a gating signal.
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公开(公告)号:US20230178008A1
公开(公告)日:2023-06-08
申请号:US18103710
申请日:2023-01-31
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Yong YUAN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/061 , G09G2320/0233
Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module, a data write module, a compensation module and a reset module. The drive module includes a drive transistor; the data write module is connected to a first electrode of the drive transistor; the compensation module is connected between a gate of the drive transistor and a second electrode of the drive transistor; and the reset module is connected to the gate of the drive transistor or the second electrode of the drive transistor. The working process of the pixel circuit includes a first bias adjustment stage, and the first bias adjustment stage includes a first stage; and in the first stage, the data write module and the reset module are turned off, and the compensation module is turned on.
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公开(公告)号:US20250054445A1
公开(公告)日:2025-02-13
申请号:US18805754
申请日:2024-08-15
Applicant: Xiamen Tianma Display Technology Co., Ltd.
Inventor: Yong YUAN
IPC: G09G3/3233
Abstract: Provided are a display panel and a display device. The display panel includes a first driver circuit and a pixel circuit. The first driver circuit is configured to provide a first drive signal for the pixel circuit, where the first drive signal includes a first sub-drive signal and a second sub-drive signal. The first driver circuit includes a first driving portion and a second driving portion. The first driving portion includes the K-th stage to the L-th stage of shift registers and is configured to output the first sub-drive signal, and the second driving portion includes the M-th stage to the N-th stage of shift registers and is configured to output the second sub-drive signal. The pulse change frequency of the first sub-drive signal is F1, and the pulse change frequency of the second sub-drive signal is F2, where F1≠F2.
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