公开(公告)号：US20190173493A1

公开(公告)日：2019-06-06

申请号：US16169659

申请日：2018-10-24

Applicant: Xieon Networks S.a.r.l.

Inventor： Stefano CALABRÓ ,  Peter KAINZMAIER ,  Heinrich VON KIRCHBAUER

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/112 ,  H03M13/1114 ,  H03M13/114 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6566

Abstract: A decoding system for an iterative decoding of a parity check code comprises a first loop circuit adapted to store log-likelihood ratio values corresponding to a plurality of received data symbols in a memory unit; a second loop circuit adapted to compute a difference between a check-to-variable log-likelihood message at a second iteration step, and a check-to-variable log-likelihood message at a first iteration step, when the first iteration step precedes the second iteration step; and an adder unit adapted to update a log-likelihood ratio value stored on the first loop circuit by adding the difference computed in the second loop circuit; wherein the first loop circuit and the second loop circuit are synchronized such that the adder unit forwards the updated log-likelihood ratio value synchronously both to the first loop circuit and to the second loop circuit.