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公开(公告)号：US12126356B2
公开(公告)日：2024-10-22
申请号：US18334905
申请日：2023-06-14
发明人： Yutaka Murakami
CPC分类号： H03M13/1102 , H03M13/23 , H03M13/235 , H03M13/2792 , H03M13/353 , H03M13/6502 , H03M13/6516 , H04L1/0041
摘要： A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.
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公开(公告)号：US12072763B2
公开(公告)日：2024-08-27
申请号：US17661437
申请日：2022-04-29
申请人： Pure Storage, Inc.
发明人： Bruno H. Cabral , Joseph M. Kaczmarek , Ravi V. Khadiwala , Ilya Volvovski , Manish Motwani , Ethan S. Wozniak
IPC分类号： G06F11/00 , G06F3/06 , G06F9/48 , G06F9/50 , G06F11/10 , G06F11/14 , G06F12/0866 , G06F12/0891 , G06F15/173 , H03M13/11 , H03M13/15 , H03M13/37 , H04L67/1097 , H03M13/00 , H04L9/40 , H04L61/45 , H04L101/604
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0619 , G06F3/0629 , G06F3/0635 , G06F3/064 , G06F3/0644 , G06F3/0665 , G06F3/067 , G06F3/0689 , G06F9/4881 , G06F9/5083 , G06F11/108 , G06F11/1092 , G06F11/1402 , G06F11/1464 , G06F12/0866 , G06F12/0891 , G06F15/17331 , H03M13/1105 , H03M13/1515 , H03M13/3761 , H04L67/1097 , G06F2201/84 , G06F2211/1007 , G06F2212/1024 , G06F2212/154 , G06F2212/263 , G06F2212/403 , H03M13/616 , H03M13/6502 , H04L61/457 , H04L63/101 , H04L2101/604
摘要： A computing device includes an interface configured to interface and communicate with a storage network, a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device receives a data access request for an encoded data slice associated with a data object, determines whether the encoded data slice is stored in the first memory and in response to a determination that the encoded data slice is not stored in the first memory, issues another data access request for the encoded data slice to a second memory, where the first memory includes access characteristics that are faster than the second memory. When a data access response including the encoded data slice is received from the second memory, a response including the encoded data slice is transmitted.
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3.发明公开公开(公告)号：US20230361789A1
公开(公告)日：2023-11-09
申请号：US18029351
申请日：2021-05-14
申请人： LG ELECTRONICS INC.
发明人： Sungjin KIM , Byoung Hoon KIM , Kyung Ho LEE , Jaehoon CHUNG , Jongwoong SHIN
CPC分类号： H03M13/6561 , H03M13/6502 , H03M13/13
摘要： The present disclosure a method of operating user equipment (UE) in a wireless communication system, the method comprising: identifying layer information that is applied to a neural polar code; generating, based on the identified layer information, transmission data by encoding data that is input into the neural polar code; and transmitting the transmission data to a base station, wherein, based on polar code transformation, the neural polar code generates the transmission data by performing encoding, based on the polar code transformation, from an initial layer of the data to a first layer according to the identified layer information and by performing encoding through a neural network-based autoencoder after the first layer until the transmission data is generated.
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公开(公告)号：US20230327685A1
公开(公告)日：2023-10-12
申请号：US18334905
申请日：2023-06-14
发明人： Yutaka MURAKAMI
CPC分类号： H03M13/2792 , H03M13/1102 , H03M13/23 , H03M13/235 , H03M13/353 , H03M13/6502 , H03M13/6516 , H04L1/0041
摘要： A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.
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公开(公告)号：US20190190543A1
公开(公告)日：2019-06-20
申请号：US15849590
申请日：2017-12-20
发明人： Chi-Yuen Young , Jaeyoung Kwak
CPC分类号： H03M13/616 , H03M13/1105 , H03M13/1137 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/6502 , H03M13/6516 , H03M13/6561 , H04L1/0041 , H04L1/0045
摘要： Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.
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公开(公告)号：US20190097656A1
公开(公告)日：2019-03-28
申请号：US15903604
申请日：2018-02-23
申请人： SK hynix Inc.
发明人： Aman Bhatia , Naveen Kumar , Abhiram Prabhakar , Chenrong Xiong , Fan Zhang
CPC分类号： H03M13/1117 , H03M13/1108 , H03M13/112 , H03M13/1131 , H03M13/1177 , H03M13/616 , H03M13/6502
摘要： Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value.
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公开(公告)号：US20190068319A1
公开(公告)日：2019-02-28
申请号：US15683456
申请日：2017-08-22
发明人： YARON SHANY , Jun-Jin Kong
CPC分类号： H04L1/0043 , H03M13/1515 , H03M13/153 , H03M13/453 , H03M13/6502
摘要： An application specific integrated circuit (ASIC) tangibly encodes a program of instructions executable by the integrated circuit to perform a method for fast Chase decoding of generalized Reed-Solomon (GRS) codes. The method includes using outputs of a syndrome-based hard-decision (HD) algorithm to find an initial Groebner basis G for a solution module of a key equation, upon failure of HD decoding of a GRS codeword received by the ASIC from a communication channel; traversing a tree of error patterns on a plurality of unreliable coordinates to adjoin a next weak coordinate, where vertices of the tree of error patterns correspond to error patterns, and edges connect a parent error pattern to a child error pattern having exactly one additional non-zero value, to find a Groebner basis for each adjoining error location; and outputting an estimated transmitted codeword when a correct error vector has been found.
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公开(公告)号：US20180287640A1
公开(公告)日：2018-10-04
申请号：US15937503
申请日：2018-03-27
发明人： Jaime Menjay Lin , Yang Yang , Gabi Sarkis , Rotem Cooper , John Edward Smee
CPC分类号： H03M13/3746 , H03M13/13 , H03M13/6502 , H04L1/0041 , H04L1/0054 , H04L1/0057
摘要： Techniques are described to address run-time issues and other considerations of data structure reorganization operations executed while decoding a polar code. A receiving entity (e.g., a user equipment or a base station) may partition an array, or other data structure, into sections. The array may be used during a list decoding operation of a polar code. As the array is populated with path elements for candidate paths, each section may be organized and a permutation pattern calculated for each section. Upon identifying a section reorganization event, the array or subsections of the array may be reorganized according the permutation patterns determined for each section.
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公开(公告)号：US20180262212A1
公开(公告)日：2018-09-13
申请号：US15976175
申请日：2018-05-10
申请人： STREAMSCALE, INC.
发明人： Michael H. Anderson
IPC分类号： H03M13/15 , H04L1/00 , G06F11/10 , H03M13/00 , H03M13/37 , H03M13/13 , H03M13/11 , G11C29/52 , G06F12/06 , G06F12/02
CPC分类号： H03M13/154 , G06F11/1068 , G06F11/1076 , G06F11/1092 , G06F11/1096 , G06F12/0238 , G06F12/06 , G06F2211/1057 , G06F2211/109 , G11C29/52 , H03M13/1191 , H03M13/134 , H03M13/1515 , H03M13/373 , H03M13/3761 , H03M13/3776 , H03M13/616 , H03M13/6502 , H04L1/0043 , H04L1/0057
摘要： An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
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公开(公告)号：US10020825B1
公开(公告)日：2018-07-10
申请号：US14964791
申请日：2015-12-10
申请人： MBIT WIRELESS, INC.
发明人： Bhaskar Patel
CPC分类号： H03M13/3707 , H03M13/2957 , H03M13/2975 , H03M13/6502 , H03M13/6525
摘要： Turbo codes are used for high throughput and high performance communication systems. Turbo codes are a class of codes that can be decoded iteratively for high performance. The iterative decoding leads to increased processing requirements which in turn requires a higher clock speed. A turbo decoder that can support the worst case clock speed requirement may lead to high power consumption. A method and apparatus are disclosed that enable high performance turbo decoding while keeping the required clock speed and the power consumption low.
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