公开(公告)号：US20240193227A1

公开(公告)日：2024-06-13

申请号：US18076602

申请日：2022-12-07

Applicant: Xilinx, Inc.

Inventor： Abhishek Kumar Jain ,  Dinesh Gaitonde

IPC: G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544

CPC classification number: G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G06F7/5443

Abstract: Partition-level compression of an m×n sparse matrix includes determining in each partition, row and column indices of elements having non-zero values. Each partition has s rows and t columns and s

公开(公告)号：US12079484B2

公开(公告)日：2024-09-03

申请号：US18230117

申请日：2023-08-03

Applicant: XILINX, INC.

Inventor： Abhishek Kumar Jain ,  Henri Fraisse ,  Dinesh D. Gaitonde

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

公开(公告)号：US20230267169A1

公开(公告)日：2023-08-24

申请号：US17679887

申请日：2022-02-24

Applicant: Xilinx, Inc.

Inventor： Abhishek Kumar Jain ,  Dinesh Gaitonde

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Circuitry for multiplying a sparse matrix by a dense vector includes a first switching circuit (302) for routing input triplets from N input ports to N output ports based on column indices of the triplets. Each triplet includes a non-zero value, a row index, and a column index. N first memory banks (303) store subsets of vector elements and are addressed by the column indices of the triplets. N multipliers (305) multiply the non-zero values of the triplets by the vector element read from the respective memory bank. A second switching circuit (304) routes tuples based on row indices of the tuples. Each tuple includes a product output by the one of the N multipliers and a row index output by an output port of the first switching circuit. N accumulator circuits (307) sum products of tuples having equal row indices.

公开(公告)号：US11720255B1

公开(公告)日：2023-08-08

申请号：US17184458

申请日：2021-02-24

Applicant: XILINX, INC.

Inventor： Abhishek Kumar Jain ,  Henri Fraisse ,  Dinesh D. Gaitonde

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.