公开(公告)号：US10068045B1

公开(公告)日：2018-09-04

申请号：US15374994

申请日：2016-12-09

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Chiwei Huang

IPC: G06F17/50

Abstract: A programmable logic design is generated for a programmable logic device (PLD) containing configurable logic blocks (CLBs) each having a plurality of multiplexers and look-up-table (LUT) circuits. A first subset of multiplexers are identified from the plurality of multiplexers based upon an analysis of design definitions for input signals of the plurality of multiplexers. The first subset of multiplexers are transformed into LUT logic. Configuration data is generated that is designed to be loaded into the PLD to configure the CLBs. The configuration data includes the LUT logic.