公开(公告)号：US20250005246A1

公开(公告)日：2025-01-02

申请号：US18345393

申请日：2023-06-30

Applicant: Xilinx, Inc.

Inventor： Chia-Jui Hsu ,  Fnu Sindhoori

IPC: G06F30/337 ,  G06F16/22

Abstract: Compiling a tensor specification for multi-dimensional direct memory access circuit configurations includes generating a first list of tile combination objects from a tensor tiling specification. The first list specifies a sequence of tiles specified by the tensor tiling specification in which each tile object represents a single tile of a tensor data structure. A second list of tile combination objects is generated by combining selected ones of the tile combination objects from the first list. Each tile combination object of the second list represents one or more tile objects. The tile combination objects of the second list are converted into buffer descriptor objects that include buffer descriptor parameters. Each of the buffer descriptor objects that is non-compliant with hardware constraints corresponding to a data mover circuit that is configurable using the buffer descriptor objects is legalized. The buffer descriptor objects are output, as legalized.