Extracting system architecture in high level synthesis
    1.
    发明授权
    Extracting system architecture in high level synthesis 有权
    在高级综合中提取系统架构

    公开(公告)号:US09449131B2

    公开(公告)日:2016-09-20

    申请号:US14294062

    申请日:2014-06-02

    Applicant: Xilinx, Inc.

    Abstract: Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.

    Abstract translation: 在高级合成中提取系统架构包括确定高级编程语言描述的第一函数和包含在高级编程描述的控制流结构内的第二函数。 第二功能被确定为第一功能的数据消耗功能。 在电路设计中,自动生成包括本地存储器的端口。 端口将第一功能的第一电路块实现耦合到电路设计内的第二功能的第二电路块实现。

    EXTRACTING SYSTEM ARCHITECTURE IN HIGH LEVEL SYNTHESIS
    2.
    发明申请
    EXTRACTING SYSTEM ARCHITECTURE IN HIGH LEVEL SYNTHESIS 有权
    高级合成中的提取体系结构

    公开(公告)号:US20150347654A1

    公开(公告)日:2015-12-03

    申请号:US14294062

    申请日:2014-06-02

    Applicant: Xilinx, Inc.

    Abstract: Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.

    Abstract translation: 在高级合成中提取系统架构包括确定高级编程语言描述的第一函数和包含在高级编程描述的控制流结构内的第二函数。 第二功能被确定为第一功能的数据消耗功能。 在电路设计中,自动生成包括本地存储器的端口。 端口将第一功能的第一电路块实现耦合到电路设计内的第二功能的第二电路块实现。

    Throughput during high level synthesis
    3.
    发明授权
    Throughput during high level synthesis 有权
    高水平合成期间的吞吐量

    公开(公告)号:US09081930B1

    公开(公告)日:2015-07-14

    申请号:US14450544

    申请日:2014-08-04

    Applicant: Xilinx, Inc.

    CPC classification number: G06F17/505 G06F11/261 G06F17/5045

    Abstract: Improving throughput during high level synthesis includes determining a data dependency for a flow control construct of a high level programming language description and translating the high level programming language description into a circuit design specifying circuitry for implementation within an integrated circuit. The circuitry is pipelined. As part of the circuit design and using a processor, a stall detection circuit is generated. The stall detection circuit is coupled to selectively initiate a stall of a stalling portion of the circuitry according to the data dependency.

    Abstract translation: 在高级合成期间提高吞吐量包括确定用于高级编程语言描述的流控制结构的数据依赖性,并将高级编程语言描述转换成用于在集成电路内实现的电路设计指定电路。 电路是流水线的。 作为电路设计和使用处理器的一部分,产生了失速检测电路。 失速检测电路被耦合以根据数据依赖性选择性地启动电路的停滞部分的失速。

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