公开(公告)号：US08881079B1

公开(公告)日：2014-11-04

申请号：US13797771

申请日：2013-03-12

Applicant: Xilinx, Inc.

Inventor： Peichen Pan ,  Chang'an Ye ,  Kecheng Hao

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/505

Abstract: An embodiment of a method of high-level synthesis of a dataflow pipeline is disclosed. This embodiment includes obtaining processes from the high-level synthesis of the dataflow pipeline. A schedule for read operations and write operations for first-in, first-out data channels of the processes is determined. A dataflow through the dataflow pipeline for the schedule is determined. An edge-weighted directed acyclic graph for the processes and the dataflow is generated. A longest path in the edge-weighted directed acyclic graph is located. A weight for the longest path is output as an estimate, such as a latency estimate for example, for the dataflow.

Abstract translation: 公开了一种数据流管线的高级合成方法的实施例。 该实施例包括从数据流管线的高级合成获得处理。 确定用于进程的先入先出数据信道的读操作和写操作的调度。 确定通过数据流管道的数据流进度表。 生成用于进程和数据流的边缘加权有向非循环图。 位于边缘加权有向非循环图中的最长路径。 输出最长路径的权重作为估计，例如数据流的等待时间估计。

公开(公告)号：US09081930B1

公开(公告)日：2015-07-14

申请号：US14450544

申请日：2014-08-04

Applicant: Xilinx, Inc.

Inventor： Stephen A. Neuendorffer ,  Kecheng Hao ,  Guoling Han

IPC: G06F17/50 ,  G06F11/26

CPC classification number: G06F17/505 ,  G06F11/261 ,  G06F17/5045

Abstract: Improving throughput during high level synthesis includes determining a data dependency for a flow control construct of a high level programming language description and translating the high level programming language description into a circuit design specifying circuitry for implementation within an integrated circuit. The circuitry is pipelined. As part of the circuit design and using a processor, a stall detection circuit is generated. The stall detection circuit is coupled to selectively initiate a stall of a stalling portion of the circuitry according to the data dependency.

Abstract translation: 在高级合成期间提高吞吐量包括确定用于高级编程语言描述的流控制结构的数据依赖性，并将高级编程语言描述转换成用于在集成电路内实现的电路设计指定电路。 电路是流水线的。 作为电路设计和使用处理器的一部分，产生了失速检测电路。 失速检测电路被耦合以根据数据依赖性选择性地启动电路的停滞部分的失速。

公开(公告)号：US09824172B1

公开(公告)日：2017-11-21

申请号：US15078400

申请日：2016-03-23

Applicant: Xilinx, Inc.

Inventor： Kecheng Hao ,  Hongbin Zheng ,  Stephen A. Neuendorffer

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Implementing circuitry from an application can include determining a data flow of an application including a producer function, a loop construct, and a consumer function and creating a new function including contents of a body of the loop construct. A circuit design can be generated from the application including a producer function circuit block, a new function circuit block, and a consumer function circuit block. Control circuitry for each circuit block can be included within the circuit design. The control circuitry of the new function circuit block can initiate operation of the new function circuit block according to a loop induction variable of the loop construct.

公开(公告)号：US09710584B1

公开(公告)日：2017-07-18

申请号：US15078347

申请日：2016-03-23

Applicant: Xilinx, Inc.

Inventor： Kecheng Hao ,  Hongbin Zheng ,  Stephen A. Neuendorffer

IPC: G06F17/50 ,  G06F3/06

CPC classification number: G06F17/505 ,  G06F8/443

Abstract: Implementing circuitry from an application may include partitioning an array of the application into a plurality of virtual blocks according to a streaming dimension of the array and determining that a first function and a second function of the application that access the array have same access patterns for the virtual blocks of the array. A first-in-first out (FIFO) memory may be included in a circuit design implementing the application. The FIFO memory couples a first circuit block implementing the first function with a second circuit block implementing the second function. Control circuitry is included within the circuit design. The control circuitry may be configured to implement concurrent operation of the first circuit block and the second circuit block by controlling accesses of the first circuit block and the second circuit block to a plurality of buffers in the FIFO memory.