公开(公告)号：US10747502B2

公开(公告)日：2020-08-18

申请号：US16136041

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Satyaprakash Pareek ,  Anup Hosangadi ,  Bing Tian ,  Ashish Sirasao ,  Yao Fu ,  Oscar Fernando C. Fernandez ,  Michael Wu ,  Christopher H. Dick

IPC: G06F7/544 ,  G06F7/499 ,  G06F9/30 ,  G06F9/38

Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.

公开(公告)号：US20200089472A1

公开(公告)日：2020-03-19

申请号：US16136041

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Satyaprakash Pareek ,  Anup Hosangadi ,  Bing Tian ,  Ashish Sirasao ,  Yao Fu ,  Oscar Fernando C. Fernandez ,  Michael Wu ,  Christopher H. Dick

IPC: G06F7/499 ,  G06F7/544 ,  G06F9/38 ,  G06F9/30

Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.