公开(公告)号：US11604758B2

公开(公告)日：2023-03-14

申请号：US17096742

申请日：2020-11-12

Applicant: Xilinx, Inc.

Inventor： Peng Zhang ,  Cody Hao Yu ,  Xuechao Wei ,  Peichen Pan

IPC: G06F9/30 ,  G06F15/80 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Systems and methods for automated systolic array design from a high-level program are disclosed. One implementation of a systolic array design supporting a convolutional neural network includes a two-dimensional array of reconfigurable processing elements arranged in rows and columns. Each processing element has an associated SIMD vector and is connected through a local connection to at least one other processing element. An input feature map buffer having a double buffer is configured to store input feature maps, and an interconnect system is configured to pass data to neighboring processing elements in accordance with a processing element scheduler. A CNN computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.

公开(公告)号：US11429767B2

公开(公告)日：2022-08-30

申请号：US16723091

申请日：2019-12-20

Applicant: Xilinx, Inc.

Inventor： Cody Hao Yu ,  Peng Zhang

IPC: G06F9/44 ,  G06F30/27 ,  G06F30/34 ,  G06N20/10 ,  G06F9/54 ,  G06F9/50

Abstract: Systems and methods for designing an information processing system are described. In one embodiment, a design space is partitioned into a plurality of independent partitions based on a defined set of rules. A unique processing core is assigned to each partition. A plurality of starting points is generated for each partition, where each starting point is associated with a machine learning algorithm. The starting points for each partition may include a performance driven seed and an area-driven seed. A set of feasible designs associated with the information processing system are determined.