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公开(公告)号：US20240144897A1
公开(公告)日：2024-05-02
申请号：US17979499
申请日：2022-11-02
Applicant: Xilinx, Inc.
Inventor： Killivalavan Kaliyamoorthy , Nedunuri Venkata Pattabhi Sai Ram , Phani Krishna Kondepudi , Kapil Usgaonkar , Pankaj Vasant Kumbhare
CPC classification number: G09G5/399 , G09G5/18 , H04N5/44504
Abstract: A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.
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公开(公告)号：US12183311B2
公开(公告)日：2024-12-31
申请号：US17979499
申请日：2022-11-02
Applicant: Xilinx, Inc.
Inventor： Killivalavan Kaliyamoorthy , Nedunuri Venkata Pattabhi Sai Ram , Phani Krishna Kondepudi , Kapil Usgaonkar , Pankaj Vasant Kumbhare
Abstract: A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.
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