公开(公告)号：US09222976B1

公开(公告)日：2015-12-29

申请号：US14745860

申请日：2015-06-22

Applicant: Xilinx, Inc.

Inventor： Kapil Usgaonkar

IPC: H03K19/00 ,  G01R31/3177

CPC classification number: G01R31/3177

Abstract: Various example implementations are directed to circuits and methods for debugging multiple integrated circuit (IC) packages. According to an example implementation, a first logic analyzer in a first IC package determines a latency of a data link. In response to test input data, the first logic analyzer communicates the test input data to a second IC package, via the data link, and captures a first set of data signals from a logic circuit in the first IC package. In response to test input data, a second logic analyzer in the second IC package captures a second set of data signals from a second logic circuit and communicates the second set of data signals to the first logic analyzer circuit via the data link. The first logic analyzer aligns the first and second sets of data signals, based on the determined latency, and outputs the aligned sets of data signals.

Abstract translation: 各种示例实现涉及用于调试多个集成电路（IC）封装的电路和方法。 根据示例实现，第一IC封装中的第一逻辑分析器确定数据链路的等待时间。 响应于测试输入数据，第一逻辑分析仪经由数据链路将测试输入数据传送到第二IC封装，并从第一IC封装中的逻辑电路捕获第一组数据信号。 响应于测试输入数据，第二IC封装中的第二逻辑分析器从第二逻辑电路捕获第二组数据信号，并经由数据链路将第二组数据信号传送到第一逻辑分析器电路。 第一逻辑分析仪基于所确定的等待时间来对准第一组数据信号和第二组数据信号，并输出对准的数据信号组。

公开(公告)号：US12183311B2

公开(公告)日：2024-12-31

申请号：US17979499

申请日：2022-11-02

Applicant: Xilinx, Inc.

Inventor： Killivalavan Kaliyamoorthy ,  Nedunuri Venkata Pattabhi Sai Ram ,  Phani Krishna Kondepudi ,  Kapil Usgaonkar ,  Pankaj Vasant Kumbhare

IPC: G09G5/399 ,  G09G5/18 ,  H04N5/445

Abstract: A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.

公开(公告)号：US20240144897A1

公开(公告)日：2024-05-02

申请号：US17979499

申请日：2022-11-02

Applicant: Xilinx, Inc.

Inventor： Killivalavan Kaliyamoorthy ,  Nedunuri Venkata Pattabhi Sai Ram ,  Phani Krishna Kondepudi ,  Kapil Usgaonkar ,  Pankaj Vasant Kumbhare

IPC: G09G5/399 ,  G09G5/18 ,  H04N5/445

CPC classification number: G09G5/399 ,  G09G5/18 ,  H04N5/44504

Abstract: A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.

公开(公告)号：US10078113B1

公开(公告)日：2018-09-18

申请号：US14736790

申请日：2015-06-11

Applicant: Xilinx, Inc.

Inventor： Kapil Usgaonkar ,  Niloy Roy

IPC: G01R31/28 ,  G06F11/00 ,  G01R31/3177

CPC classification number: G01R31/31705 ,  G06F11/322 ,  G06F11/364

Abstract: Various example implementations are directed to circuits and methods for debugging logic circuits utilizing a data bus for communication. According to an example implementation, an apparatus includes a logic circuit configured to communicate data over a data bus according to a communication protocol. The apparatus also includes a logic analyzer circuit coupled to the data bus. The logic analyzer circuit is configured to capture, in response to a control signal, samples of data signals communicated on the data bus. The logic analyzer circuit determines respective pairs of start and end positions of the data transactions in the captured samples. The logic analyzer circuit outputs the samples of the data signals and a set of metadata including the determined pairs of start and end positions of data transactions in the samples.