公开(公告)号：US12254253B2

公开(公告)日：2025-03-18

申请号：US17520087

申请日：2021-11-05

Applicant: Xilinx, Inc.

Inventor： Suman Kumar Timmireddy ,  Jaipal Reddy Nareddy ,  Rahul Kunwar ,  Adithya Balaji Boda

IPC: G06F30/31 ,  G06Q50/18 ,  G06F115/08

Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.

公开(公告)号：US20230144285A1

公开(公告)日：2023-05-11

申请号：US17520087

申请日：2021-11-05

Applicant: Xilinx, Inc.

Inventor： Suman Kumar Timmireddy ,  Jaipal Reddy Nareddy ,  Rahul Kunwar ,  Adithya Balaji Boda

IPC: G06F30/31 ,  G06Q50/18

CPC classification number: G06F30/31 ,  G06Q50/184 ,  G06F2115/08

Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.