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    Post-synthesis insertion of debug cores
    1.
    发明授权
    Post-synthesis insertion of debug cores 有权

    公开(公告)号：US10949586B1

    公开(公告)日：2021-03-16

    申请号：US16918228

    申请日：2020-07-01

    Applicant: Xilinx, Inc.

    Inventor： Jaipal R. Nareddy ,  Suman Kumar Timmireddy ,  Rahul Gupta

    IPC: G06F30/327 ,  G06F30/394 ,  G06F115/02

    Abstract: Approaches for post-synthesis insertion of debug cores include a programmed processor inputting data that identify signals of a synthesized circuit design to be probed and determining whether or not debug cores and interfaces needed to probe the signals are absent from the circuit design. The programmed processor creates, in response to determining that the debug cores and interfaces are absent, the debug cores and interfaces in the circuit design. The programmed processor couples the debug cores and interfaces to the signals in the circuit design and synthesizes the debug cores and interfaces created in the circuit design to create a modified circuit design. The method includes generating a circuit definition from the modified circuit design by the programmed processor, and implementing a circuit that operates according to the circuit definition.

    Programmable IC design creation using circuit board data
    3.
    发明授权
    Programmable IC design creation using circuit board data 有权
    使用电路板数据创建可编程IC设计

    公开(公告)号：US09465903B1

    公开(公告)日：2016-10-11

    申请号：US14546684

    申请日：2014-11-18

    Applicant: Xilinx, Inc.

    Inventor： Suman Kumar Timmireddy ,  Heera Nand ,  Awdhesh Kumar Sahu ,  Brendan M. O'Higgins ,  David A. Knol ,  Siddharth Rele

    IPC: G06F17/50 ,  G06F19/00 ,  H03K19/177 ,  G06F21/12 ,  G06F15/78

    CPC classification number: G06F17/5054 ,  G06F15/7867 ,  G06F17/50 ,  G06F17/5022 ,  G06F21/125 ,  H03K19/17728 ,  H03K19/17748

    Abstract: A method of implementing a circuit design in a circuit design tool for configuration in a programmable integrated circuit (IC) connected to components on a circuit board is described. The method includes processing a first file associated with the circuit board to obtain descriptions of circuit board interfaces of the components on the circuit board; displaying a graphic user interface (GUI) of the circuit design tool to connect a circuit board interface described in the first file with a circuit design interface in the circuit design; generating physical constraints on the circuit design interface with respect to input/outputs of the programmable IC described as being connected to the selected circuit board interface; and generating a bitstream to configure the programmable IC. The bitstream includes a physical implementation of the circuit design satisfying the physical constraints.

    Abstract translation: 描述了在用于配置在与电路板上的部件连接的可编程集成电路（IC）中的电路设计工具中实现电路设计的方法。 该方法包括处理与电路板相关联的第一文件以获得电路板上组件的电路板接口的描述; 显示所述电路设计工具的图形用户界面（GUI），以将所述第一文件中描述的电路板接口与所述电路设计中的电路设计接口连接; 相对于被描述为连接到所选择的电路板接口的可编程IC的输入/输出，在电路设计接口上产生物理约束; 以及生成比特流以配置可编程IC。 比特流包括满足物理约束的电路设计的物理实现。

    Resource estimation for implementing circuit designs within an integrated circuit
    4.
    发明授权
    Resource estimation for implementing circuit designs within an integrated circuit 有权

    公开(公告)号：US12254253B2

    公开(公告)日：2025-03-18

    申请号：US17520087

    申请日：2021-11-05

    Applicant: Xilinx, Inc.

    Inventor： Suman Kumar Timmireddy ,  Jaipal Reddy Nareddy ,  Rahul Kunwar ,  Adithya Balaji Boda

    IPC: G06F30/31 ,  G06Q50/18 ,  G06F115/08

    Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.

    RESOURCE ESTIMATION FOR IMPLEMENTING CIRCUIT DESIGNS WITHIN AN INTEGRATED CIRCUIT
    6.
    发明公开
    RESOURCE ESTIMATION FOR IMPLEMENTING CIRCUIT DESIGNS WITHIN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230144285A1

    公开(公告)日：2023-05-11

    申请号：US17520087

    申请日：2021-11-05

    Applicant: Xilinx, Inc.

    Inventor： Suman Kumar Timmireddy ,  Jaipal Reddy Nareddy ,  Rahul Kunwar ,  Adithya Balaji Boda

    IPC: G06F30/31 ,  G06Q50/18

    CPC classification number: G06F30/31 ,  G06Q50/184 ,  G06F2115/08

    Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.

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