公开(公告)号：US20230044581A1

公开(公告)日：2023-02-09

申请号：US17394714

申请日：2021-08-05

Applicant: Xilinx, Inc.

Inventor： Tim Tuan ,  Seokjoong Kim ,  Sai Anirudh Jayanthi

IPC: G06F30/20 ,  G06F1/06 ,  G06F1/28 ,  G06F12/02

Abstract: Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an instruction-based power model executed by the computer hardware, a based on the pipeline snapshot data. The plurality of estimates of power consumption are calculated using the instruction-based power model based on the plurality of snapshots over the plurality of clock cycles.