公开(公告)号：US10162916B1

公开(公告)日：2018-12-25

申请号：US15433766

申请日：2017-02-15

Applicant: Xilinx, Inc.

Inventor： Usha Narasimha ,  Atul Srinivasan ,  Nagaraj Savithri

IPC: G06F17/50 ,  G06F17/11

Abstract: Disclosed approaches for processing a circuit design targeted to a programmable integrated circuit (IC) include inputting the circuit design to a programmed processor. Each path of the circuit design specifies a plurality of circuit elements of the programmable IC. For each circuit element specified in a path of the plurality of paths the processor looks up in a memory a mean delay associated with the circuit element, looks up a sigma factor associated with the circuit element, and looks up a delta factor associated with the circuit element. The processor determines a delay of the path as a function of the mean delay, sigma factor, and delta factor of each circuit element in the path.

公开(公告)号：US10203718B1

公开(公告)日：2019-02-12

申请号：US15192299

申请日：2016-06-24

Applicant: Xilinx, Inc.

Inventor： Usha Narasimha

IPC: G06F1/12 ,  G06F1/10

Abstract: Generating delays for a clock circuit includes, determining, using a processor, groups of contexts for exit points of the clock circuit based upon a plurality of characteristics and a type selected from a plurality of different types for each characteristic, forming, using the processor, sub-groups of the exit points based upon delay values for the exit points, and determining, using the processor, a mean delay value for each sub-group.