公开(公告)号：US20230376662A1

公开(公告)日：2023-11-23

申请号：US17746512

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： Nageshwar Reddy Peddamgari ,  Sourabh Anand ,  Vasudha Annam ,  Chandra Sekhar Mulpuri

IPC: G06F30/3308

CPC classification number: G06F30/3308

Abstract: Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective behavioral simulation model of the particular component in the overall simulation model is replaced with the RTL simulation model, and a simulation that executes the overall simulation model and the RTL simulation model in place of the behavioral simulation model of the particular component is performed.